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https://git.suyu.dev/suyu/suyu.git
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ef24e72b26
Involves making asserts use printf instead of the log functions (log functions are asynchronous and, as such, the log won't be printed in time) As such, the log type argument was removed (printf obviously can't use it, and it's made obsolete by the file and line printing) Also removed some GEKKO cruft.
601 lines
23 KiB
C++
601 lines
23 KiB
C++
// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <stack>
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#include <boost/range/algorithm.hpp>
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#include <common/file_util.h>
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#include <core/mem_map.h>
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#include <nihstro/shader_bytecode.h>
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#include "pica.h"
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#include "vertex_shader.h"
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#include "debug_utils/debug_utils.h"
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using nihstro::Instruction;
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using nihstro::RegisterType;
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using nihstro::SourceRegister;
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using nihstro::SwizzlePattern;
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namespace Pica {
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namespace VertexShader {
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static struct {
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Math::Vec4<float24> f[96];
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std::array<bool,16> b;
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std::array<Math::Vec4<u8>,4> i;
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} shader_uniforms;
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// TODO: Not sure where the shader binary and swizzle patterns are supposed to be loaded to!
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// For now, we just keep these local arrays around.
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static std::array<u32, 1024> shader_memory;
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static std::array<u32, 1024> swizzle_data;
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void SubmitShaderMemoryChange(u32 addr, u32 value) {
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shader_memory[addr] = value;
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}
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void SubmitSwizzleDataChange(u32 addr, u32 value) {
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swizzle_data[addr] = value;
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}
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Math::Vec4<float24>& GetFloatUniform(u32 index) {
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return shader_uniforms.f[index];
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}
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bool& GetBoolUniform(u32 index) {
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return shader_uniforms.b[index];
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}
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Math::Vec4<u8>& GetIntUniform(u32 index) {
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return shader_uniforms.i[index];
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}
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const std::array<u32, 1024>& GetShaderBinary() {
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return shader_memory;
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}
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const std::array<u32, 1024>& GetSwizzlePatterns() {
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return swizzle_data;
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}
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struct VertexShaderState {
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u32* program_counter;
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const float24* input_register_table[16];
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float24* output_register_table[7*4];
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Math::Vec4<float24> temporary_registers[16];
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bool conditional_code[2];
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// Two Address registers and one loop counter
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// TODO: How many bits do these actually have?
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s32 address_registers[3];
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enum {
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INVALID_ADDRESS = 0xFFFFFFFF
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};
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struct CallStackElement {
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u32 final_address;
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u32 return_address;
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};
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// TODO: Is there a maximal size for this?
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std::stack<CallStackElement> call_stack;
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struct {
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u32 max_offset; // maximum program counter ever reached
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u32 max_opdesc_id; // maximum swizzle pattern index ever used
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} debug;
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};
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static void ProcessShaderCode(VertexShaderState& state) {
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// Placeholder for invalid inputs
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static float24 dummy_vec4_float24[4];
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while (true) {
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if (!state.call_stack.empty()) {
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if (state.program_counter - shader_memory.data() == state.call_stack.top().final_address) {
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state.program_counter = &shader_memory[state.call_stack.top().return_address];
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state.call_stack.pop();
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// TODO: Is "trying again" accurate to hardware?
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continue;
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}
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}
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bool exit_loop = false;
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const Instruction& instr = *(const Instruction*)state.program_counter;
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const SwizzlePattern& swizzle = *(SwizzlePattern*)&swizzle_data[instr.common.operand_desc_id];
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auto call = [&](VertexShaderState& state, u32 offset, u32 num_instructions, u32 return_offset) {
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state.program_counter = &shader_memory[offset] - 1; // -1 to make sure when incrementing the PC we end up at the correct offset
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state.call_stack.push({ offset + num_instructions, return_offset });
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};
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u32 binary_offset = state.program_counter - shader_memory.data();
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state.debug.max_offset = std::max<u32>(state.debug.max_offset, 1 + binary_offset);
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auto LookupSourceRegister = [&](const SourceRegister& source_reg) -> const float24* {
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switch (source_reg.GetRegisterType()) {
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case RegisterType::Input:
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return state.input_register_table[source_reg.GetIndex()];
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case RegisterType::Temporary:
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return &state.temporary_registers[source_reg.GetIndex()].x;
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case RegisterType::FloatUniform:
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return &shader_uniforms.f[source_reg.GetIndex()].x;
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default:
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return dummy_vec4_float24;
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}
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};
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switch (instr.opcode.GetInfo().type) {
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case Instruction::OpCodeType::Arithmetic:
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{
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bool is_inverted = 0 != (instr.opcode.GetInfo().subtype & Instruction::OpCodeInfo::SrcInversed);
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// TODO: We don't really support this properly: For instance, the address register
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// offset needs to be applied to SRC2 instead, etc.
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// For now, we just abort in this situation.
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ASSERT_MSG(!is_inverted, "Bad condition...");
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const int address_offset = (instr.common.address_register_index == 0)
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? 0 : state.address_registers[instr.common.address_register_index - 1];
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const float24* src1_ = LookupSourceRegister(instr.common.GetSrc1(is_inverted) + address_offset);
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const float24* src2_ = LookupSourceRegister(instr.common.GetSrc2(is_inverted));
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const bool negate_src1 = ((bool)swizzle.negate_src1 != false);
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const bool negate_src2 = ((bool)swizzle.negate_src2 != false);
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float24 src1[4] = {
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src1_[(int)swizzle.GetSelectorSrc1(0)],
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src1_[(int)swizzle.GetSelectorSrc1(1)],
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src1_[(int)swizzle.GetSelectorSrc1(2)],
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src1_[(int)swizzle.GetSelectorSrc1(3)],
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};
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if (negate_src1) {
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src1[0] = src1[0] * float24::FromFloat32(-1);
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src1[1] = src1[1] * float24::FromFloat32(-1);
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src1[2] = src1[2] * float24::FromFloat32(-1);
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src1[3] = src1[3] * float24::FromFloat32(-1);
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}
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float24 src2[4] = {
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src2_[(int)swizzle.GetSelectorSrc2(0)],
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src2_[(int)swizzle.GetSelectorSrc2(1)],
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src2_[(int)swizzle.GetSelectorSrc2(2)],
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src2_[(int)swizzle.GetSelectorSrc2(3)],
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};
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if (negate_src2) {
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src2[0] = src2[0] * float24::FromFloat32(-1);
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src2[1] = src2[1] * float24::FromFloat32(-1);
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src2[2] = src2[2] * float24::FromFloat32(-1);
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src2[3] = src2[3] * float24::FromFloat32(-1);
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}
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float24* dest = (instr.common.dest < 0x08) ? state.output_register_table[4*instr.common.dest.GetIndex()]
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: (instr.common.dest < 0x10) ? dummy_vec4_float24
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: (instr.common.dest < 0x20) ? &state.temporary_registers[instr.common.dest.GetIndex()][0]
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: dummy_vec4_float24;
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state.debug.max_opdesc_id = std::max<u32>(state.debug.max_opdesc_id, 1+instr.common.operand_desc_id);
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switch (instr.opcode.EffectiveOpCode()) {
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case Instruction::OpCode::ADD:
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{
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = src1[i] + src2[i];
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}
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break;
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}
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case Instruction::OpCode::MUL:
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{
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = src1[i] * src2[i];
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}
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break;
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}
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case Instruction::OpCode::MAX:
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = std::max(src1[i], src2[i]);
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}
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break;
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case Instruction::OpCode::DP3:
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case Instruction::OpCode::DP4:
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{
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float24 dot = float24::FromFloat32(0.f);
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int num_components = (instr.opcode == Instruction::OpCode::DP3) ? 3 : 4;
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for (int i = 0; i < num_components; ++i)
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dot = dot + src1[i] * src2[i];
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for (int i = 0; i < num_components; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = dot;
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}
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break;
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}
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// Reciprocal
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case Instruction::OpCode::RCP:
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{
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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// TODO: Be stable against division by zero!
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// TODO: I think this might be wrong... we should only use one component here
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dest[i] = float24::FromFloat32(1.0 / src1[i].ToFloat32());
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}
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break;
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}
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// Reciprocal Square Root
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case Instruction::OpCode::RSQ:
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{
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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// TODO: Be stable against division by zero!
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// TODO: I think this might be wrong... we should only use one component here
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dest[i] = float24::FromFloat32(1.0 / sqrt(src1[i].ToFloat32()));
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}
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break;
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}
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case Instruction::OpCode::MOVA:
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{
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for (int i = 0; i < 2; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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// TODO: Figure out how the rounding is done on hardware
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state.address_registers[i] = static_cast<s32>(src1[i].ToFloat32());
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}
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break;
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}
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case Instruction::OpCode::MOV:
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{
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = src1[i];
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}
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break;
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}
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case Instruction::OpCode::CMP:
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for (int i = 0; i < 2; ++i) {
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// TODO: Can you restrict to one compare via dest masking?
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auto compare_op = instr.common.compare_op;
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auto op = (i == 0) ? compare_op.x.Value() : compare_op.y.Value();
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switch (op) {
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case compare_op.Equal:
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state.conditional_code[i] = (src1[i] == src2[i]);
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break;
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case compare_op.NotEqual:
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state.conditional_code[i] = (src1[i] != src2[i]);
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break;
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case compare_op.LessThan:
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state.conditional_code[i] = (src1[i] < src2[i]);
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break;
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case compare_op.LessEqual:
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state.conditional_code[i] = (src1[i] <= src2[i]);
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break;
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case compare_op.GreaterThan:
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state.conditional_code[i] = (src1[i] > src2[i]);
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break;
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case compare_op.GreaterEqual:
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state.conditional_code[i] = (src1[i] >= src2[i]);
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break;
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default:
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LOG_ERROR(HW_GPU, "Unknown compare mode %x", static_cast<int>(op));
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break;
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}
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}
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break;
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default:
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LOG_ERROR(HW_GPU, "Unhandled arithmetic instruction: 0x%02x (%s): 0x%08x",
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(int)instr.opcode.Value(), instr.opcode.GetInfo().name, instr.hex);
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DEBUG_ASSERT(false);
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break;
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}
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break;
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}
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case Instruction::OpCodeType::MultiplyAdd:
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{
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if (instr.opcode.EffectiveOpCode() == Instruction::OpCode::MAD) {
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const SwizzlePattern& swizzle = *(SwizzlePattern*)&swizzle_data[instr.mad.operand_desc_id];
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const float24* src1_ = LookupSourceRegister(instr.mad.src1);
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const float24* src2_ = LookupSourceRegister(instr.mad.src2);
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const float24* src3_ = LookupSourceRegister(instr.mad.src3);
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const bool negate_src1 = ((bool)swizzle.negate_src1 != false);
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const bool negate_src2 = ((bool)swizzle.negate_src2 != false);
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const bool negate_src3 = ((bool)swizzle.negate_src3 != false);
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float24 src1[4] = {
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src1_[(int)swizzle.GetSelectorSrc1(0)],
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src1_[(int)swizzle.GetSelectorSrc1(1)],
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src1_[(int)swizzle.GetSelectorSrc1(2)],
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src1_[(int)swizzle.GetSelectorSrc1(3)],
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};
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if (negate_src1) {
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src1[0] = src1[0] * float24::FromFloat32(-1);
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src1[1] = src1[1] * float24::FromFloat32(-1);
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src1[2] = src1[2] * float24::FromFloat32(-1);
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src1[3] = src1[3] * float24::FromFloat32(-1);
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}
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float24 src2[4] = {
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src2_[(int)swizzle.GetSelectorSrc2(0)],
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src2_[(int)swizzle.GetSelectorSrc2(1)],
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src2_[(int)swizzle.GetSelectorSrc2(2)],
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src2_[(int)swizzle.GetSelectorSrc2(3)],
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};
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if (negate_src2) {
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src2[0] = src2[0] * float24::FromFloat32(-1);
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src2[1] = src2[1] * float24::FromFloat32(-1);
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src2[2] = src2[2] * float24::FromFloat32(-1);
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src2[3] = src2[3] * float24::FromFloat32(-1);
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}
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float24 src3[4] = {
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src3_[(int)swizzle.GetSelectorSrc3(0)],
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src3_[(int)swizzle.GetSelectorSrc3(1)],
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src3_[(int)swizzle.GetSelectorSrc3(2)],
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src3_[(int)swizzle.GetSelectorSrc3(3)],
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};
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if (negate_src3) {
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src3[0] = src3[0] * float24::FromFloat32(-1);
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src3[1] = src3[1] * float24::FromFloat32(-1);
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src3[2] = src3[2] * float24::FromFloat32(-1);
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src3[3] = src3[3] * float24::FromFloat32(-1);
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}
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float24* dest = (instr.mad.dest < 0x08) ? state.output_register_table[4*instr.mad.dest.GetIndex()]
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: (instr.mad.dest < 0x10) ? dummy_vec4_float24
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: (instr.mad.dest < 0x20) ? &state.temporary_registers[instr.mad.dest.GetIndex()][0]
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: dummy_vec4_float24;
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = src1[i] * src2[i] + src3[i];
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}
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} else {
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LOG_ERROR(HW_GPU, "Unhandled multiply-add instruction: 0x%02x (%s): 0x%08x",
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(int)instr.opcode.Value(), instr.opcode.GetInfo().name, instr.hex);
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}
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break;
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}
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default:
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{
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static auto evaluate_condition = [](const VertexShaderState& state, bool refx, bool refy, Instruction::FlowControlType flow_control) {
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bool results[2] = { refx == state.conditional_code[0],
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refy == state.conditional_code[1] };
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switch (flow_control.op) {
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case flow_control.Or:
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return results[0] || results[1];
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case flow_control.And:
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return results[0] && results[1];
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case flow_control.JustX:
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return results[0];
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case flow_control.JustY:
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return results[1];
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}
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};
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// Handle each instruction on its own
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switch (instr.opcode) {
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case Instruction::OpCode::END:
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exit_loop = true;
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break;
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case Instruction::OpCode::JMPC:
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if (evaluate_condition(state, instr.flow_control.refx, instr.flow_control.refy, instr.flow_control)) {
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state.program_counter = &shader_memory[instr.flow_control.dest_offset] - 1;
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}
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break;
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case Instruction::OpCode::JMPU:
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if (shader_uniforms.b[instr.flow_control.bool_uniform_id]) {
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state.program_counter = &shader_memory[instr.flow_control.dest_offset] - 1;
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}
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break;
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case Instruction::OpCode::CALL:
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call(state,
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instr.flow_control.dest_offset,
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instr.flow_control.num_instructions,
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binary_offset + 1);
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break;
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case Instruction::OpCode::CALLU:
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if (shader_uniforms.b[instr.flow_control.bool_uniform_id]) {
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call(state,
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instr.flow_control.dest_offset,
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instr.flow_control.num_instructions,
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binary_offset + 1);
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}
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break;
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case Instruction::OpCode::CALLC:
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if (evaluate_condition(state, instr.flow_control.refx, instr.flow_control.refy, instr.flow_control)) {
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call(state,
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instr.flow_control.dest_offset,
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instr.flow_control.num_instructions,
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binary_offset + 1);
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}
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break;
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case Instruction::OpCode::NOP:
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break;
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case Instruction::OpCode::IFU:
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if (shader_uniforms.b[instr.flow_control.bool_uniform_id]) {
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call(state,
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binary_offset + 1,
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instr.flow_control.dest_offset - binary_offset - 1,
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instr.flow_control.dest_offset + instr.flow_control.num_instructions);
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} else {
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call(state,
|
|
instr.flow_control.dest_offset,
|
|
instr.flow_control.num_instructions,
|
|
instr.flow_control.dest_offset + instr.flow_control.num_instructions);
|
|
}
|
|
|
|
break;
|
|
|
|
case Instruction::OpCode::IFC:
|
|
{
|
|
// TODO: Do we need to consider swizzlers here?
|
|
|
|
if (evaluate_condition(state, instr.flow_control.refx, instr.flow_control.refy, instr.flow_control)) {
|
|
call(state,
|
|
binary_offset + 1,
|
|
instr.flow_control.dest_offset - binary_offset - 1,
|
|
instr.flow_control.dest_offset + instr.flow_control.num_instructions);
|
|
} else {
|
|
call(state,
|
|
instr.flow_control.dest_offset,
|
|
instr.flow_control.num_instructions,
|
|
instr.flow_control.dest_offset + instr.flow_control.num_instructions);
|
|
}
|
|
|
|
break;
|
|
}
|
|
|
|
default:
|
|
LOG_ERROR(HW_GPU, "Unhandled instruction: 0x%02x (%s): 0x%08x",
|
|
(int)instr.opcode.Value(), instr.opcode.GetInfo().name, instr.hex);
|
|
break;
|
|
}
|
|
|
|
break;
|
|
}
|
|
}
|
|
|
|
++state.program_counter;
|
|
|
|
if (exit_loop)
|
|
break;
|
|
}
|
|
}
|
|
|
|
OutputVertex RunShader(const InputVertex& input, int num_attributes) {
|
|
VertexShaderState state;
|
|
|
|
const u32* main = &shader_memory[registers.vs_main_offset];
|
|
state.program_counter = (u32*)main;
|
|
state.debug.max_offset = 0;
|
|
state.debug.max_opdesc_id = 0;
|
|
|
|
// Setup input register table
|
|
const auto& attribute_register_map = registers.vs_input_register_map;
|
|
float24 dummy_register;
|
|
boost::fill(state.input_register_table, &dummy_register);
|
|
if(num_attributes > 0) state.input_register_table[attribute_register_map.attribute0_register] = &input.attr[0].x;
|
|
if(num_attributes > 1) state.input_register_table[attribute_register_map.attribute1_register] = &input.attr[1].x;
|
|
if(num_attributes > 2) state.input_register_table[attribute_register_map.attribute2_register] = &input.attr[2].x;
|
|
if(num_attributes > 3) state.input_register_table[attribute_register_map.attribute3_register] = &input.attr[3].x;
|
|
if(num_attributes > 4) state.input_register_table[attribute_register_map.attribute4_register] = &input.attr[4].x;
|
|
if(num_attributes > 5) state.input_register_table[attribute_register_map.attribute5_register] = &input.attr[5].x;
|
|
if(num_attributes > 6) state.input_register_table[attribute_register_map.attribute6_register] = &input.attr[6].x;
|
|
if(num_attributes > 7) state.input_register_table[attribute_register_map.attribute7_register] = &input.attr[7].x;
|
|
if(num_attributes > 8) state.input_register_table[attribute_register_map.attribute8_register] = &input.attr[8].x;
|
|
if(num_attributes > 9) state.input_register_table[attribute_register_map.attribute9_register] = &input.attr[9].x;
|
|
if(num_attributes > 10) state.input_register_table[attribute_register_map.attribute10_register] = &input.attr[10].x;
|
|
if(num_attributes > 11) state.input_register_table[attribute_register_map.attribute11_register] = &input.attr[11].x;
|
|
if(num_attributes > 12) state.input_register_table[attribute_register_map.attribute12_register] = &input.attr[12].x;
|
|
if(num_attributes > 13) state.input_register_table[attribute_register_map.attribute13_register] = &input.attr[13].x;
|
|
if(num_attributes > 14) state.input_register_table[attribute_register_map.attribute14_register] = &input.attr[14].x;
|
|
if(num_attributes > 15) state.input_register_table[attribute_register_map.attribute15_register] = &input.attr[15].x;
|
|
|
|
// Setup output register table
|
|
OutputVertex ret;
|
|
// Zero output so that attributes which aren't output won't have denormals in them, which will
|
|
// slow us down later.
|
|
memset(&ret, 0, sizeof(ret));
|
|
|
|
for (int i = 0; i < 7; ++i) {
|
|
const auto& output_register_map = registers.vs_output_attributes[i];
|
|
|
|
u32 semantics[4] = {
|
|
output_register_map.map_x, output_register_map.map_y,
|
|
output_register_map.map_z, output_register_map.map_w
|
|
};
|
|
|
|
for (int comp = 0; comp < 4; ++comp)
|
|
state.output_register_table[4*i+comp] = ((float24*)&ret) + semantics[comp];
|
|
}
|
|
|
|
state.conditional_code[0] = false;
|
|
state.conditional_code[1] = false;
|
|
|
|
ProcessShaderCode(state);
|
|
DebugUtils::DumpShader(shader_memory.data(), state.debug.max_offset, swizzle_data.data(),
|
|
state.debug.max_opdesc_id, registers.vs_main_offset,
|
|
registers.vs_output_attributes);
|
|
|
|
LOG_TRACE(Render_Software, "Output vertex: pos (%.2f, %.2f, %.2f, %.2f), col(%.2f, %.2f, %.2f, %.2f), tc0(%.2f, %.2f)",
|
|
ret.pos.x.ToFloat32(), ret.pos.y.ToFloat32(), ret.pos.z.ToFloat32(), ret.pos.w.ToFloat32(),
|
|
ret.color.x.ToFloat32(), ret.color.y.ToFloat32(), ret.color.z.ToFloat32(), ret.color.w.ToFloat32(),
|
|
ret.tc0.u().ToFloat32(), ret.tc0.v().ToFloat32());
|
|
|
|
return ret;
|
|
}
|
|
|
|
|
|
} // namespace
|
|
|
|
} // namespace
|