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108 lines
No EOL
4.4 KiB
C++
108 lines
No EOL
4.4 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "video_core/engines/shader_bytecode.h"
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#include "video_core/shader/shader_ir.h"
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namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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u32 ShaderIR::DecodeXmad(BasicBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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UNIMPLEMENTED_IF(instr.xmad.sign_a);
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UNIMPLEMENTED_IF(instr.xmad.sign_b);
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in XMAD is not implemented");
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Node op_a = GetRegister(instr.gpr8); // instr.xmad.sign_a
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// TODO(bunnei): Needs to be fixed once op_a or op_b is signed
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UNIMPLEMENTED_IF(instr.xmad.sign_a != instr.xmad.sign_b);
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const bool is_signed_a = instr.xmad.sign_a == 1;
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const bool is_signed_b = instr.xmad.sign_b == 1;
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const bool is_signed_c = is_signed_a;
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auto [is_merge, op_b, op_c] = [&]() -> std::tuple<bool, Node, Node> {
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switch (opcode->get().GetId()) {
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case OpCode::Id::XMAD_CR:
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return {instr.xmad.merge_56, GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset),
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GetRegister(instr.gpr39)};
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case OpCode::Id::XMAD_RR:
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return {instr.xmad.merge_37, GetRegister(instr.gpr20), GetRegister(instr.gpr39)};
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case OpCode::Id::XMAD_RC:
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return {false, GetRegister(instr.gpr39),
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GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset)};
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case OpCode::Id::XMAD_IMM:
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return {instr.xmad.merge_37, Immediate(static_cast<u32>(instr.xmad.imm20_16)),
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GetRegister(instr.gpr39)};
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default:
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UNIMPLEMENTED_MSG("Unhandled XMAD instruction: {}", opcode->get().GetName());
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}
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}();
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if (instr.xmad.high_a) {
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op_a = SignedOperation(OperationCode::ILogicalShiftRight, is_signed_a, NO_PRECISE, op_a,
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Immediate(16));
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} else {
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op_a = SignedOperation(OperationCode::IBitwiseAnd, is_signed_a, NO_PRECISE, op_a,
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Immediate(0xffff));
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}
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const Node original_b = op_b;
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if (instr.xmad.high_b) {
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op_b = SignedOperation(OperationCode::ILogicalShiftRight, is_signed_b, NO_PRECISE, op_a,
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Immediate(16));
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} else {
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op_b = SignedOperation(OperationCode::IBitwiseAnd, is_signed_b, NO_PRECISE, op_b,
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Immediate(0xffff));
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}
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// TODO(Rodrigo): Use an appropiate sign for this operation
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Node product = Operation(OperationCode::IMul, NO_PRECISE, op_a, op_b);
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if (instr.xmad.product_shift_left) {
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product = Operation(OperationCode::ILogicalShiftLeft, NO_PRECISE, op_a, Immediate(16));
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}
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op_c = [&]() {
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switch (instr.xmad.mode) {
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case Tegra::Shader::XmadMode::None:
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return op_c;
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case Tegra::Shader::XmadMode::CLo:
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return SignedOperation(OperationCode::IBitwiseAnd, is_signed_c, NO_PRECISE, op_c,
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Immediate(0xffff));
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case Tegra::Shader::XmadMode::CHi:
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return SignedOperation(OperationCode::ILogicalShiftRight, is_signed_c, NO_PRECISE, op_c,
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Immediate(16));
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case Tegra::Shader::XmadMode::CBcc: {
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const Node shifted_b = SignedOperation(OperationCode::ILogicalShiftLeft, is_signed_b,
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NO_PRECISE, original_b, Immediate(16));
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return SignedOperation(OperationCode::IAdd, is_signed_c, NO_PRECISE, op_c, shifted_b);
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}
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default: {
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UNIMPLEMENTED_MSG("Unhandled XMAD mode: {}", static_cast<u32>(instr.xmad.mode.Value()));
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}
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}
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}();
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// TODO(Rodrigo): Use an appropiate sign for this operation
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Node sum = Operation(OperationCode::IAdd, product, op_c);
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if (is_merge) {
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const Node a = Operation(OperationCode::IBitwiseAnd, NO_PRECISE, sum, Immediate(0xffff));
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const Node b =
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Operation(OperationCode::ILogicalShiftLeft, NO_PRECISE, original_b, Immediate(0xffff));
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sum = Operation(OperationCode::IBitwiseOr, NO_PRECISE, a, b);
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}
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SetRegister(bb, instr.gpr0, sum);
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return pc;
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}
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} // namespace VideoCommon::Shader
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