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262 lines
11 KiB
C++
262 lines
11 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "common/logging/log.h"
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#include "video_core/engines/shader_bytecode.h"
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#include "video_core/shader/node_helper.h"
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#include "video_core/shader/shader_ir.h"
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namespace VideoCommon::Shader {
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using Tegra::Shader::ConditionCode;
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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using Tegra::Shader::Register;
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using Tegra::Shader::SystemVariable;
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u32 ShaderIR::DecodeOther(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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switch (opcode->get().GetId()) {
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case OpCode::Id::NOP: {
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UNIMPLEMENTED_IF(instr.nop.cc != Tegra::Shader::ConditionCode::T);
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UNIMPLEMENTED_IF(instr.nop.trigger != 0);
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// With the previous preconditions, this instruction is a no-operation.
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break;
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}
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case OpCode::Id::EXIT: {
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const Tegra::Shader::ConditionCode cc = instr.flow_condition_code;
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UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, "EXIT condition code used: {}",
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static_cast<u32>(cc));
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switch (instr.flow.cond) {
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case Tegra::Shader::FlowCondition::Always:
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bb.push_back(Operation(OperationCode::Exit));
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if (instr.pred.pred_index == static_cast<u64>(Tegra::Shader::Pred::UnusedIndex)) {
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// If this is an unconditional exit then just end processing here,
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// otherwise we have to account for the possibility of the condition
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// not being met, so continue processing the next instruction.
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pc = MAX_PROGRAM_LENGTH - 1;
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}
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break;
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case Tegra::Shader::FlowCondition::Fcsm_Tr:
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// TODO(bunnei): What is this used for? If we assume this conditon is not
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// satisifed, dual vertex shaders in Farming Simulator make more sense
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UNIMPLEMENTED_MSG("Skipping unknown FlowCondition::Fcsm_Tr");
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break;
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default:
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UNIMPLEMENTED_MSG("Unhandled flow condition: {}",
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static_cast<u32>(instr.flow.cond.Value()));
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}
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break;
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}
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case OpCode::Id::KIL: {
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UNIMPLEMENTED_IF(instr.flow.cond != Tegra::Shader::FlowCondition::Always);
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const Tegra::Shader::ConditionCode cc = instr.flow_condition_code;
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UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, "KIL condition code used: {}",
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static_cast<u32>(cc));
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bb.push_back(Operation(OperationCode::Discard));
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break;
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}
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case OpCode::Id::MOV_SYS: {
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const Node value = [&]() {
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switch (instr.sys20) {
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case SystemVariable::Ydirection:
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return Operation(OperationCode::YNegate);
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case SystemVariable::InvocationInfo:
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LOG_WARNING(HW_GPU, "MOV_SYS instruction with InvocationInfo is incomplete");
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return Immediate(0u);
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case SystemVariable::TidX:
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return Operation(OperationCode::LocalInvocationIdX);
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case SystemVariable::TidY:
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return Operation(OperationCode::LocalInvocationIdY);
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case SystemVariable::TidZ:
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return Operation(OperationCode::LocalInvocationIdZ);
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case SystemVariable::CtaIdX:
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return Operation(OperationCode::WorkGroupIdX);
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case SystemVariable::CtaIdY:
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return Operation(OperationCode::WorkGroupIdY);
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case SystemVariable::CtaIdZ:
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return Operation(OperationCode::WorkGroupIdZ);
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default:
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UNIMPLEMENTED_MSG("Unhandled system move: {}",
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static_cast<u32>(instr.sys20.Value()));
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return Immediate(0u);
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}
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}();
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::BRA: {
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Node branch;
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if (instr.bra.constant_buffer == 0) {
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const u32 target = pc + instr.bra.GetBranchTarget();
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branch = Operation(OperationCode::Branch, Immediate(target));
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} else {
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const u32 target = pc + 1;
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const Node op_a = GetConstBuffer(instr.cbuf36.index, instr.cbuf36.GetOffset());
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const Node convert = SignedOperation(OperationCode::IArithmeticShiftRight, true,
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PRECISE, op_a, Immediate(3));
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const Node operand =
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Operation(OperationCode::IAdd, PRECISE, convert, Immediate(target));
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branch = Operation(OperationCode::BranchIndirect, operand);
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}
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const Tegra::Shader::ConditionCode cc = instr.flow_condition_code;
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if (cc != Tegra::Shader::ConditionCode::T) {
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bb.push_back(Conditional(GetConditionCode(cc), {branch}));
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} else {
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bb.push_back(branch);
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}
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break;
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}
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case OpCode::Id::BRX: {
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Node operand;
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if (instr.brx.constant_buffer != 0) {
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const s32 target = pc + 1;
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const Node index = GetRegister(instr.gpr8);
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const Node op_a =
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GetConstBufferIndirect(instr.cbuf36.index, instr.cbuf36.GetOffset() + 0, index);
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const Node convert = SignedOperation(OperationCode::IArithmeticShiftRight, true,
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PRECISE, op_a, Immediate(3));
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operand = Operation(OperationCode::IAdd, PRECISE, convert, Immediate(target));
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} else {
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const s32 target = pc + instr.brx.GetBranchExtend();
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const Node op_a = GetRegister(instr.gpr8);
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const Node convert = SignedOperation(OperationCode::IArithmeticShiftRight, true,
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PRECISE, op_a, Immediate(3));
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operand = Operation(OperationCode::IAdd, PRECISE, convert, Immediate(target));
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}
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const Node branch = Operation(OperationCode::BranchIndirect, operand);
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const Tegra::Shader::ConditionCode cc = instr.flow_condition_code;
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if (cc != Tegra::Shader::ConditionCode::T) {
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bb.push_back(Conditional(GetConditionCode(cc), {branch}));
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} else {
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bb.push_back(branch);
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}
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break;
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}
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case OpCode::Id::SSY: {
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UNIMPLEMENTED_IF_MSG(instr.bra.constant_buffer != 0,
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"Constant buffer flow is not supported");
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if (disable_flow_stack) {
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break;
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}
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// The SSY opcode tells the GPU where to re-converge divergent execution paths with SYNC.
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const u32 target = pc + instr.bra.GetBranchTarget();
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bb.push_back(
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Operation(OperationCode::PushFlowStack, MetaStackClass::Ssy, Immediate(target)));
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break;
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}
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case OpCode::Id::PBK: {
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UNIMPLEMENTED_IF_MSG(instr.bra.constant_buffer != 0,
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"Constant buffer PBK is not supported");
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if (disable_flow_stack) {
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break;
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}
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// PBK pushes to a stack the address where BRK will jump to.
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const u32 target = pc + instr.bra.GetBranchTarget();
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bb.push_back(
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Operation(OperationCode::PushFlowStack, MetaStackClass::Pbk, Immediate(target)));
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break;
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}
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case OpCode::Id::SYNC: {
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const Tegra::Shader::ConditionCode cc = instr.flow_condition_code;
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UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, "SYNC condition code used: {}",
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static_cast<u32>(cc));
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if (disable_flow_stack) {
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break;
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}
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// The SYNC opcode jumps to the address previously set by the SSY opcode
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bb.push_back(Operation(OperationCode::PopFlowStack, MetaStackClass::Ssy));
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break;
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}
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case OpCode::Id::BRK: {
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const Tegra::Shader::ConditionCode cc = instr.flow_condition_code;
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UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, "BRK condition code used: {}",
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static_cast<u32>(cc));
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if (disable_flow_stack) {
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break;
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}
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// The BRK opcode jumps to the address previously set by the PBK opcode
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bb.push_back(Operation(OperationCode::PopFlowStack, MetaStackClass::Pbk));
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break;
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}
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case OpCode::Id::IPA: {
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const bool is_physical = instr.ipa.idx && instr.gpr8.Value() != 0xff;
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const auto attribute = instr.attribute.fmt28;
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const Tegra::Shader::IpaMode input_mode{instr.ipa.interp_mode.Value(),
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instr.ipa.sample_mode.Value()};
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Node value = is_physical ? GetPhysicalInputAttribute(instr.gpr8)
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: GetInputAttribute(attribute.index, attribute.element);
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const Tegra::Shader::Attribute::Index index = attribute.index.Value();
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const bool is_generic = index >= Tegra::Shader::Attribute::Index::Attribute_0 &&
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index <= Tegra::Shader::Attribute::Index::Attribute_31;
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if (is_generic || is_physical) {
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// TODO(Blinkhawk): There are cases where a perspective attribute use PASS.
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// In theory by setting them as perspective, OpenGL does the perspective correction.
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// A way must figured to reverse the last step of it.
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if (input_mode.interpolation_mode == Tegra::Shader::IpaInterpMode::Multiply) {
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value = Operation(OperationCode::FMul, PRECISE, value, GetRegister(instr.gpr20));
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}
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}
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value = GetSaturatedFloat(value, instr.ipa.saturate);
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::OUT_R: {
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UNIMPLEMENTED_IF_MSG(instr.gpr20.Value() != Register::ZeroIndex,
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"Stream buffer is not supported");
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if (instr.out.emit) {
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// gpr0 is used to store the next address and gpr8 contains the address to emit.
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// Hardware uses pointers here but we just ignore it
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bb.push_back(Operation(OperationCode::EmitVertex));
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SetRegister(bb, instr.gpr0, Immediate(0));
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}
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if (instr.out.cut) {
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bb.push_back(Operation(OperationCode::EndPrimitive));
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}
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break;
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}
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case OpCode::Id::ISBERD: {
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UNIMPLEMENTED_IF(instr.isberd.o != 0);
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UNIMPLEMENTED_IF(instr.isberd.skew != 0);
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UNIMPLEMENTED_IF(instr.isberd.shift != Tegra::Shader::IsberdShift::None);
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UNIMPLEMENTED_IF(instr.isberd.mode != Tegra::Shader::IsberdMode::None);
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LOG_WARNING(HW_GPU, "ISBERD instruction is incomplete");
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SetRegister(bb, instr.gpr0, GetRegister(instr.gpr8));
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break;
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}
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case OpCode::Id::DEPBAR: {
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LOG_WARNING(HW_GPU, "DEPBAR instruction is stubbed");
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Unhandled instruction: {}", opcode->get().GetName());
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}
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return pc;
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}
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} // namespace VideoCommon::Shader
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