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104 lines
2.8 KiB
C++
104 lines
2.8 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <array>
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#include "common/assert.h"
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "video_core/gpu.h"
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#include "video_core/memory_manager.h"
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namespace Tegra {
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namespace Engines {
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#define FERMI2D_REG_INDEX(field_name) \
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(offsetof(Tegra::Engines::Fermi2D::Regs, field_name) / sizeof(u32))
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class Fermi2D final {
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public:
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explicit Fermi2D(MemoryManager& memory_manager);
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~Fermi2D() = default;
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/// Write the value to the register identified by method.
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void WriteReg(u32 method, u32 value);
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struct Regs {
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static constexpr size_t NUM_REGS = 0x258;
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struct Surface {
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RenderTargetFormat format;
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BitField<0, 1, u32> linear;
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union {
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BitField<0, 4, u32> block_depth;
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BitField<4, 4, u32> block_height;
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BitField<8, 4, u32> block_width;
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};
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u32 depth;
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u32 layer;
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u32 pitch;
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u32 width;
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u32 height;
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u32 address_high;
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u32 address_low;
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
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address_low);
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}
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};
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static_assert(sizeof(Surface) == 0x28, "Surface has incorrect size");
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enum class Operation : u32 {
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SrcCopyAnd = 0,
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ROPAnd = 1,
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Blend = 2,
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SrcCopy = 3,
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ROP = 4,
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SrcCopyPremult = 5,
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BlendPremult = 6,
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};
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union {
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struct {
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INSERT_PADDING_WORDS(0x80);
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Surface dst;
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INSERT_PADDING_WORDS(2);
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Surface src;
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INSERT_PADDING_WORDS(0x15);
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Operation operation;
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INSERT_PADDING_WORDS(0x9);
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// TODO(Subv): This is only a guess.
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u32 trigger;
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INSERT_PADDING_WORDS(0x1A3);
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};
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std::array<u32, NUM_REGS> reg_array;
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};
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} regs{};
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MemoryManager& memory_manager;
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};
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#define ASSERT_REG_POSITION(field_name, position) \
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static_assert(offsetof(Fermi2D::Regs, field_name) == position * 4, \
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(dst, 0x80);
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ASSERT_REG_POSITION(src, 0x8C);
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ASSERT_REG_POSITION(operation, 0xAB);
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ASSERT_REG_POSITION(trigger, 0xB5);
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#undef ASSERT_REG_POSITION
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} // namespace Engines
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} // namespace Tegra
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