stuff/suyu
stuff/suyu
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/suyu.git synced 2024-11-29 14:57:41 -05:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

armstate: Correct FIQ register banking

Browse source 
FIQ has seven banked registers (R8 to R14), not two.
This commit is contained in:
Lioncash 2016-03-21 05:50:05 -04:00
parent b83e95727f
commit d53c9cde1a
1 changed files with 3 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
src/core/arm/skyeye_common/armstate.cpp
View file

@ -2,6 +2,7 @@
// Licensed under GPLv2 or any later version // Licensed under GPLv2 or any later version
// Refer to the license.txt file included. // Refer to the license.txt file included.
#include <algorithm>
#include "common/swap.h" #include "common/swap.h"
#include "common/logging/log.h" #include "common/logging/log.h"
#include "core/memory.h" #include "core/memory.h"
@ -48,8 +49,7 @@ void ARMul_State::ChangePrivilegeMode(u32 new_mode)
Spsr[UNDEFBANK] = Spsr_copy; Spsr[UNDEFBANK] = Spsr_copy;
break; break;
case FIQ32MODE: case FIQ32MODE:
Reg_firq[0] = Reg[13]; std::copy(Reg.begin() + 8, Reg.end() - 1, Reg_firq.begin());
Reg_firq[1] = Reg[14];
Spsr[FIQBANK] = Spsr_copy; Spsr[FIQBANK] = Spsr_copy;
break; break;
} }
@ -85,8 +85,7 @@ void ARMul_State::ChangePrivilegeMode(u32 new_mode)
Bank = UNDEFBANK; Bank = UNDEFBANK;
break; break;
case FIQ32MODE: case FIQ32MODE:
Reg[13] = Reg_firq[0]; std::copy(Reg_firq.begin(), Reg_firq.end(), Reg.begin() + 8);
Reg[14] = Reg_firq[1];
Spsr_copy = Spsr[FIQBANK]; Spsr_copy = Spsr[FIQBANK];
Bank = FIQBANK; Bank = FIQBANK;
break; break;