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https://git.suyu.dev/suyu/suyu.git
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Merge pull request #2429 from FernandoS27/compute
Corrections and Implementation on GPU Engines
This commit is contained in:
bunnei
GitHub
commit
c27b81cb85
13 changed files with 484 additions and 143 deletions
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@ -3,6 +3,8 @@ add_library(video_core STATIC
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dma_pusher.h
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debug_utils/debug_utils.cpp
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debug_utils/debug_utils.h
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engines/engine_upload.cpp
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engines/engine_upload.h
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engines/fermi_2d.cpp
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engines/fermi_2d.h
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engines/kepler_compute.cpp
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48
src/video_core/engines/engine_upload.cpp
Normal file
48
src/video_core/engines/engine_upload.cpp
Normal file
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@ -0,0 +1,48 @@
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// Copyright 2019 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/assert.h"
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#include "video_core/engines/engine_upload.h"
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#include "video_core/memory_manager.h"
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#include "video_core/textures/decoders.h"
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namespace Tegra::Engines::Upload {
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State::State(MemoryManager& memory_manager, Registers& regs)
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: memory_manager(memory_manager), regs(regs) {}
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void State::ProcessExec(const bool is_linear) {
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write_offset = 0;
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copy_size = regs.line_length_in * regs.line_count;
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inner_buffer.resize(copy_size);
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this->is_linear = is_linear;
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}
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void State::ProcessData(const u32 data, const bool is_last_call) {
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const u32 sub_copy_size = std::min(4U, copy_size - write_offset);
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std::memcpy(&inner_buffer[write_offset], &data, sub_copy_size);
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write_offset += sub_copy_size;
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if (!is_last_call) {
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return;
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}
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const GPUVAddr address{regs.dest.Address()};
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if (is_linear) {
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memory_manager.WriteBlock(address, inner_buffer.data(), copy_size);
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} else {
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UNIMPLEMENTED_IF(regs.dest.z != 0);
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UNIMPLEMENTED_IF(regs.dest.depth != 1);
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UNIMPLEMENTED_IF(regs.dest.BlockWidth() != 1);
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UNIMPLEMENTED_IF(regs.dest.BlockDepth() != 1);
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const std::size_t dst_size = Tegra::Texture::CalculateSize(
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true, 1, regs.dest.width, regs.dest.height, 1, regs.dest.BlockHeight(), 1);
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tmp_buffer.resize(dst_size);
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memory_manager.ReadBlock(address, tmp_buffer.data(), dst_size);
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Tegra::Texture::SwizzleKepler(regs.dest.width, regs.dest.height, regs.dest.x, regs.dest.y,
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regs.dest.BlockHeight(), copy_size, inner_buffer.data(),
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tmp_buffer.data());
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memory_manager.WriteBlock(address, tmp_buffer.data(), dst_size);
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}
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}
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} // namespace Tegra::Engines::Upload
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75
src/video_core/engines/engine_upload.h
Normal file
75
src/video_core/engines/engine_upload.h
Normal file
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@ -0,0 +1,75 @@
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// Copyright 2019 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <cstddef>
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#include <vector>
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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namespace Tegra {
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class MemoryManager;
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}
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namespace Tegra::Engines::Upload {
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struct Registers {
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u32 line_length_in;
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u32 line_count;
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struct {
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u32 address_high;
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u32 address_low;
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u32 pitch;
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union {
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BitField<0, 4, u32> block_width;
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BitField<4, 4, u32> block_height;
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BitField<8, 4, u32> block_depth;
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};
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u32 width;
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u32 height;
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u32 depth;
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u32 z;
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u32 x;
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u32 y;
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) | address_low);
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}
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u32 BlockWidth() const {
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return 1U << block_width.Value();
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}
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u32 BlockHeight() const {
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return 1U << block_height.Value();
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}
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u32 BlockDepth() const {
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return 1U << block_depth.Value();
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}
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} dest;
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};
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class State {
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public:
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State(MemoryManager& memory_manager, Registers& regs);
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~State() = default;
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void ProcessExec(const bool is_linear);
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void ProcessData(const u32 data, const bool is_last_call);
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private:
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u32 write_offset = 0;
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u32 copy_size = 0;
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std::vector<u8> inner_buffer;
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std::vector<u8> tmp_buffer;
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bool is_linear = false;
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Registers& regs;
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MemoryManager& memory_manager;
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};
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} // namespace Tegra::Engines::Upload
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@ -21,6 +21,12 @@ class RasterizerInterface;
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namespace Tegra::Engines {
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/**
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* This Engine is known as G80_2D. Documentation can be found in:
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* https://github.com/envytools/envytools/blob/master/rnndb/graph/g80_2d.xml
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* https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/nouveau/nv50/nv50_2d.xml.h
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*/
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#define FERMI2D_REG_INDEX(field_name) \
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(offsetof(Tegra::Engines::Fermi2D::Regs, field_name) / sizeof(u32))
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@ -4,12 +4,21 @@
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#include "common/assert.h"
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#include "common/logging/log.h"
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#include "core/core.h"
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#include "video_core/engines/kepler_compute.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/memory_manager.h"
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#include "video_core/rasterizer_interface.h"
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#include "video_core/renderer_base.h"
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#include "video_core/textures/decoders.h"
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namespace Tegra::Engines {
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KeplerCompute::KeplerCompute(MemoryManager& memory_manager) : memory_manager{memory_manager} {}
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KeplerCompute::KeplerCompute(Core::System& system, VideoCore::RasterizerInterface& rasterizer,
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MemoryManager& memory_manager)
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: system{system}, rasterizer{rasterizer}, memory_manager{memory_manager}, upload_state{
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memory_manager,
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regs.upload} {}
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KeplerCompute::~KeplerCompute() = default;
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@ -20,14 +29,34 @@ void KeplerCompute::CallMethod(const GPU::MethodCall& method_call) {
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regs.reg_array[method_call.method] = method_call.argument;
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switch (method_call.method) {
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case KEPLER_COMPUTE_REG_INDEX(exec_upload): {
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upload_state.ProcessExec(regs.exec_upload.linear != 0);
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break;
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}
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case KEPLER_COMPUTE_REG_INDEX(data_upload): {
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const bool is_last_call = method_call.IsLastCall();
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upload_state.ProcessData(method_call.argument, is_last_call);
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if (is_last_call) {
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system.GPU().Maxwell3D().dirty_flags.OnMemoryWrite();
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}
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break;
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}
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case KEPLER_COMPUTE_REG_INDEX(launch):
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// Abort execution since compute shaders can be used to alter game memory (e.g. CUDA
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// kernels)
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UNREACHABLE_MSG("Compute shaders are not implemented");
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ProcessLaunch();
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break;
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default:
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break;
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}
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}
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void KeplerCompute::ProcessLaunch() {
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const GPUVAddr launch_desc_loc = regs.launch_desc_loc.Address();
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memory_manager.ReadBlockUnsafe(launch_desc_loc, &launch_description,
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LaunchParams::NUM_LAUNCH_PARAMETERS * sizeof(u32));
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const GPUVAddr code_loc = regs.code_loc.Address() + launch_description.program_start;
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LOG_WARNING(HW_GPU, "Compute Kernel Execute at Address 0x{:016x}, STUBBED", code_loc);
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}
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} // namespace Tegra::Engines
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@ -6,22 +6,40 @@
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#include <array>
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#include <cstddef>
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#include <vector>
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "video_core/engines/engine_upload.h"
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#include "video_core/gpu.h"
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namespace Core {
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class System;
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}
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namespace Tegra {
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class MemoryManager;
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}
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namespace VideoCore {
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class RasterizerInterface;
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}
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namespace Tegra::Engines {
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/**
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* This Engine is known as GK104_Compute. Documentation can be found in:
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* https://github.com/envytools/envytools/blob/master/rnndb/graph/gk104_compute.xml
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* https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/nouveau/nvc0/nve4_compute.xml.h
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*/
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#define KEPLER_COMPUTE_REG_INDEX(field_name) \
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(offsetof(Tegra::Engines::KeplerCompute::Regs, field_name) / sizeof(u32))
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class KeplerCompute final {
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public:
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explicit KeplerCompute(MemoryManager& memory_manager);
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explicit KeplerCompute(Core::System& system, VideoCore::RasterizerInterface& rasterizer,
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MemoryManager& memory_manager);
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~KeplerCompute();
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static constexpr std::size_t NumConstBuffers = 8;
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@ -31,30 +49,181 @@ public:
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union {
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struct {
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INSERT_PADDING_WORDS(0xAF);
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INSERT_PADDING_WORDS(0x60);
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Upload::Registers upload;
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struct {
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union {
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BitField<0, 1, u32> linear;
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};
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} exec_upload;
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u32 data_upload;
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INSERT_PADDING_WORDS(0x3F);
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struct {
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u32 address;
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address) << 8));
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}
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} launch_desc_loc;
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INSERT_PADDING_WORDS(0x1);
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u32 launch;
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INSERT_PADDING_WORDS(0xC48);
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INSERT_PADDING_WORDS(0x4A7);
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struct {
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u32 address_high;
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u32 address_low;
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u32 limit;
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
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address_low);
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}
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} tsc;
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INSERT_PADDING_WORDS(0x3);
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struct {
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u32 address_high;
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u32 address_low;
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u32 limit;
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
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address_low);
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}
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} tic;
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INSERT_PADDING_WORDS(0x22);
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struct {
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u32 address_high;
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u32 address_low;
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
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address_low);
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}
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} code_loc;
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INSERT_PADDING_WORDS(0x3FE);
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u32 texture_const_buffer_index;
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INSERT_PADDING_WORDS(0x374);
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};
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std::array<u32, NUM_REGS> reg_array;
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};
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} regs{};
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struct LaunchParams {
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static constexpr std::size_t NUM_LAUNCH_PARAMETERS = 0x40;
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INSERT_PADDING_WORDS(0x8);
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u32 program_start;
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INSERT_PADDING_WORDS(0x2);
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BitField<30, 1, u32> linked_tsc;
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BitField<0, 31, u32> grid_dim_x;
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union {
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BitField<0, 16, u32> grid_dim_y;
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BitField<16, 16, u32> grid_dim_z;
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};
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INSERT_PADDING_WORDS(0x3);
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BitField<0, 16, u32> shared_alloc;
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BitField<0, 31, u32> block_dim_x;
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union {
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BitField<0, 16, u32> block_dim_y;
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BitField<16, 16, u32> block_dim_z;
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};
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union {
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BitField<0, 8, u32> const_buffer_enable_mask;
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BitField<29, 2, u32> cache_layout;
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} memory_config;
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INSERT_PADDING_WORDS(0x8);
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struct {
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u32 address_low;
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union {
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BitField<0, 8, u32> address_high;
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BitField<15, 17, u32> size;
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};
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high.Value()) << 32) |
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address_low);
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}
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} const_buffer_config[8];
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union {
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BitField<0, 20, u32> local_pos_alloc;
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BitField<27, 5, u32> barrier_alloc;
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};
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union {
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BitField<0, 20, u32> local_neg_alloc;
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BitField<24, 5, u32> gpr_alloc;
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};
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INSERT_PADDING_WORDS(0x11);
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} launch_description;
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struct {
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u32 write_offset = 0;
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u32 copy_size = 0;
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std::vector<u8> inner_buffer;
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} state{};
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static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32),
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"KeplerCompute Regs has wrong size");
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static_assert(sizeof(LaunchParams) == LaunchParams::NUM_LAUNCH_PARAMETERS * sizeof(u32),
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"KeplerCompute LaunchParams has wrong size");
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/// Write the value to the register identified by method.
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void CallMethod(const GPU::MethodCall& method_call);
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private:
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Core::System& system;
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VideoCore::RasterizerInterface& rasterizer;
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MemoryManager& memory_manager;
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Upload::State upload_state;
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void ProcessLaunch();
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};
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#define ASSERT_REG_POSITION(field_name, position) \
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static_assert(offsetof(KeplerCompute::Regs, field_name) == position * 4, \
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"Field " #field_name " has invalid position")
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#define ASSERT_LAUNCH_PARAM_POSITION(field_name, position) \
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static_assert(offsetof(KeplerCompute::LaunchParams, field_name) == position * 4, \
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(upload, 0x60);
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ASSERT_REG_POSITION(exec_upload, 0x6C);
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ASSERT_REG_POSITION(data_upload, 0x6D);
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ASSERT_REG_POSITION(launch, 0xAF);
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ASSERT_REG_POSITION(tsc, 0x557);
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ASSERT_REG_POSITION(tic, 0x55D);
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ASSERT_REG_POSITION(code_loc, 0x582);
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ASSERT_REG_POSITION(texture_const_buffer_index, 0x982);
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ASSERT_LAUNCH_PARAM_POSITION(program_start, 0x8);
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ASSERT_LAUNCH_PARAM_POSITION(grid_dim_x, 0xC);
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ASSERT_LAUNCH_PARAM_POSITION(shared_alloc, 0x11);
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ASSERT_LAUNCH_PARAM_POSITION(block_dim_x, 0x12);
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ASSERT_LAUNCH_PARAM_POSITION(memory_config, 0x14);
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ASSERT_LAUNCH_PARAM_POSITION(const_buffer_config, 0x1D);
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#undef ASSERT_REG_POSITION
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|
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@ -14,9 +14,8 @@
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namespace Tegra::Engines {
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KeplerMemory::KeplerMemory(Core::System& system, VideoCore::RasterizerInterface& rasterizer,
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MemoryManager& memory_manager)
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: system{system}, rasterizer{rasterizer}, memory_manager{memory_manager} {}
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KeplerMemory::KeplerMemory(Core::System& system, MemoryManager& memory_manager)
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: system{system}, memory_manager{memory_manager}, upload_state{memory_manager, regs.upload} {}
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|
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KeplerMemory::~KeplerMemory() = default;
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@ -28,46 +27,18 @@ void KeplerMemory::CallMethod(const GPU::MethodCall& method_call) {
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switch (method_call.method) {
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case KEPLERMEMORY_REG_INDEX(exec): {
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ProcessExec();
|
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upload_state.ProcessExec(regs.exec.linear != 0);
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break;
|
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}
|
||||
case KEPLERMEMORY_REG_INDEX(data): {
|
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ProcessData(method_call.argument, method_call.IsLastCall());
|
||||
const bool is_last_call = method_call.IsLastCall();
|
||||
upload_state.ProcessData(method_call.argument, is_last_call);
|
||||
if (is_last_call) {
|
||||
system.GPU().Maxwell3D().dirty_flags.OnMemoryWrite();
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void KeplerMemory::ProcessExec() {
|
||||
state.write_offset = 0;
|
||||
state.copy_size = regs.line_length_in * regs.line_count;
|
||||
state.inner_buffer.resize(state.copy_size);
|
||||
}
|
||||
|
||||
void KeplerMemory::ProcessData(u32 data, bool is_last_call) {
|
||||
const u32 sub_copy_size = std::min(4U, state.copy_size - state.write_offset);
|
||||
std::memcpy(&state.inner_buffer[state.write_offset], ®s.data, sub_copy_size);
|
||||
state.write_offset += sub_copy_size;
|
||||
if (is_last_call) {
|
||||
const GPUVAddr address{regs.dest.Address()};
|
||||
if (regs.exec.linear != 0) {
|
||||
memory_manager.WriteBlock(address, state.inner_buffer.data(), state.copy_size);
|
||||
} else {
|
||||
UNIMPLEMENTED_IF(regs.dest.z != 0);
|
||||
UNIMPLEMENTED_IF(regs.dest.depth != 1);
|
||||
UNIMPLEMENTED_IF(regs.dest.BlockWidth() != 1);
|
||||
UNIMPLEMENTED_IF(regs.dest.BlockDepth() != 1);
|
||||
const std::size_t dst_size = Tegra::Texture::CalculateSize(
|
||||
true, 1, regs.dest.width, regs.dest.height, 1, regs.dest.BlockHeight(), 1);
|
||||
std::vector<u8> tmp_buffer(dst_size);
|
||||
memory_manager.ReadBlock(address, tmp_buffer.data(), dst_size);
|
||||
Tegra::Texture::SwizzleKepler(regs.dest.width, regs.dest.height, regs.dest.x,
|
||||
regs.dest.y, regs.dest.BlockHeight(), state.copy_size,
|
||||
state.inner_buffer.data(), tmp_buffer.data());
|
||||
memory_manager.WriteBlock(address, tmp_buffer.data(), dst_size);
|
||||
}
|
||||
system.GPU().Maxwell3D().dirty_flags.OnMemoryWrite();
|
||||
}
|
||||
}
|
||||
|
||||
} // namespace Tegra::Engines
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
#include "common/bit_field.h"
|
||||
#include "common/common_funcs.h"
|
||||
#include "common/common_types.h"
|
||||
#include "video_core/engines/engine_upload.h"
|
||||
#include "video_core/gpu.h"
|
||||
|
||||
namespace Core {
|
||||
|
|
@ -20,19 +21,20 @@ namespace Tegra {
|
|||
class MemoryManager;
|
||||
}
|
||||
|
||||
namespace VideoCore {
|
||||
class RasterizerInterface;
|
||||
}
|
||||
|
||||
namespace Tegra::Engines {
|
||||
|
||||
/**
|
||||
* This Engine is known as P2MF. Documentation can be found in:
|
||||
* https://github.com/envytools/envytools/blob/master/rnndb/graph/gk104_p2mf.xml
|
||||
* https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/nouveau/nvc0/nve4_p2mf.xml.h
|
||||
*/
|
||||
|
||||
#define KEPLERMEMORY_REG_INDEX(field_name) \
|
||||
(offsetof(Tegra::Engines::KeplerMemory::Regs, field_name) / sizeof(u32))
|
||||
|
||||
class KeplerMemory final {
|
||||
public:
|
||||
KeplerMemory(Core::System& system, VideoCore::RasterizerInterface& rasterizer,
|
||||
MemoryManager& memory_manager);
|
||||
KeplerMemory(Core::System& system, MemoryManager& memory_manager);
|
||||
~KeplerMemory();
|
||||
|
||||
/// Write the value to the register identified by method.
|
||||
|
|
@ -45,42 +47,7 @@ public:
|
|||
struct {
|
||||
INSERT_PADDING_WORDS(0x60);
|
||||
|
||||
u32 line_length_in;
|
||||
u32 line_count;
|
||||
|
||||
struct {
|
||||
u32 address_high;
|
||||
u32 address_low;
|
||||
u32 pitch;
|
||||
union {
|
||||
BitField<0, 4, u32> block_width;
|
||||
BitField<4, 4, u32> block_height;
|
||||
BitField<8, 4, u32> block_depth;
|
||||
};
|
||||
u32 width;
|
||||
u32 height;
|
||||
u32 depth;
|
||||
u32 z;
|
||||
u32 x;
|
||||
u32 y;
|
||||
|
||||
GPUVAddr Address() const {
|
||||
return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
|
||||
address_low);
|
||||
}
|
||||
|
||||
u32 BlockWidth() const {
|
||||
return 1U << block_width.Value();
|
||||
}
|
||||
|
||||
u32 BlockHeight() const {
|
||||
return 1U << block_height.Value();
|
||||
}
|
||||
|
||||
u32 BlockDepth() const {
|
||||
return 1U << block_depth.Value();
|
||||
}
|
||||
} dest;
|
||||
Upload::Registers upload;
|
||||
|
||||
struct {
|
||||
union {
|
||||
|
|
@ -96,28 +63,17 @@ public:
|
|||
};
|
||||
} regs{};
|
||||
|
||||
struct {
|
||||
u32 write_offset = 0;
|
||||
u32 copy_size = 0;
|
||||
std::vector<u8> inner_buffer;
|
||||
} state{};
|
||||
|
||||
private:
|
||||
Core::System& system;
|
||||
VideoCore::RasterizerInterface& rasterizer;
|
||||
MemoryManager& memory_manager;
|
||||
|
||||
void ProcessExec();
|
||||
void ProcessData(u32 data, bool is_last_call);
|
||||
Upload::State upload_state;
|
||||
};
|
||||
|
||||
#define ASSERT_REG_POSITION(field_name, position) \
|
||||
static_assert(offsetof(KeplerMemory::Regs, field_name) == position * 4, \
|
||||
"Field " #field_name " has invalid position")
|
||||
|
||||
ASSERT_REG_POSITION(line_length_in, 0x60);
|
||||
ASSERT_REG_POSITION(line_count, 0x61);
|
||||
ASSERT_REG_POSITION(dest, 0x62);
|
||||
ASSERT_REG_POSITION(upload, 0x60);
|
||||
ASSERT_REG_POSITION(exec, 0x6C);
|
||||
ASSERT_REG_POSITION(data, 0x6D);
|
||||
#undef ASSERT_REG_POSITION
|
||||
|
|
|
|||
|
|
@ -20,8 +20,8 @@ constexpr u32 MacroRegistersStart = 0xE00;
|
|||
|
||||
Maxwell3D::Maxwell3D(Core::System& system, VideoCore::RasterizerInterface& rasterizer,
|
||||
MemoryManager& memory_manager)
|
||||
: system{system}, rasterizer{rasterizer}, memory_manager{memory_manager}, macro_interpreter{
|
||||
*this} {
|
||||
: system{system}, rasterizer{rasterizer}, memory_manager{memory_manager},
|
||||
macro_interpreter{*this}, upload_state{memory_manager, regs.upload} {
|
||||
InitializeRegisterDefaults();
|
||||
}
|
||||
|
||||
|
|
@ -253,6 +253,18 @@ void Maxwell3D::CallMethod(const GPU::MethodCall& method_call) {
|
|||
ProcessSyncPoint();
|
||||
break;
|
||||
}
|
||||
case MAXWELL3D_REG_INDEX(exec_upload): {
|
||||
upload_state.ProcessExec(regs.exec_upload.linear != 0);
|
||||
break;
|
||||
}
|
||||
case MAXWELL3D_REG_INDEX(data_upload): {
|
||||
const bool is_last_call = method_call.IsLastCall();
|
||||
upload_state.ProcessData(method_call.argument, is_last_call);
|
||||
if (is_last_call) {
|
||||
dirty_flags.OnMemoryWrite();
|
||||
}
|
||||
break;
|
||||
}
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
#include "common/common_funcs.h"
|
||||
#include "common/common_types.h"
|
||||
#include "common/math_util.h"
|
||||
#include "video_core/engines/engine_upload.h"
|
||||
#include "video_core/gpu.h"
|
||||
#include "video_core/macro_interpreter.h"
|
||||
#include "video_core/textures/texture.h"
|
||||
|
|
@ -32,6 +33,12 @@ class RasterizerInterface;
|
|||
|
||||
namespace Tegra::Engines {
|
||||
|
||||
/**
|
||||
* This Engine is known as GF100_3D. Documentation can be found in:
|
||||
* https://github.com/envytools/envytools/blob/master/rnndb/graph/gf100_3d.xml
|
||||
* https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/nouveau/nvc0/nvc0_3d.xml.h
|
||||
*/
|
||||
|
||||
#define MAXWELL3D_REG_INDEX(field_name) \
|
||||
(offsetof(Tegra::Engines::Maxwell3D::Regs, field_name) / sizeof(u32))
|
||||
|
||||
|
|
@ -580,7 +587,18 @@ public:
|
|||
u32 bind;
|
||||
} macros;
|
||||
|
||||
INSERT_PADDING_WORDS(0x69);
|
||||
INSERT_PADDING_WORDS(0x17);
|
||||
|
||||
Upload::Registers upload;
|
||||
struct {
|
||||
union {
|
||||
BitField<0, 1, u32> linear;
|
||||
};
|
||||
} exec_upload;
|
||||
|
||||
u32 data_upload;
|
||||
|
||||
INSERT_PADDING_WORDS(0x44);
|
||||
|
||||
struct {
|
||||
union {
|
||||
|
|
@ -1176,6 +1194,8 @@ private:
|
|||
/// Interpreter for the macro codes uploaded to the GPU.
|
||||
MacroInterpreter macro_interpreter;
|
||||
|
||||
Upload::State upload_state;
|
||||
|
||||
/// Retrieves information about a specific TIC entry from the TIC buffer.
|
||||
Texture::TICEntry GetTICEntry(u32 tic_index) const;
|
||||
|
||||
|
|
@ -1219,6 +1239,9 @@ private:
|
|||
"Field " #field_name " has invalid position")
|
||||
|
||||
ASSERT_REG_POSITION(macros, 0x45);
|
||||
ASSERT_REG_POSITION(upload, 0x60);
|
||||
ASSERT_REG_POSITION(exec_upload, 0x6C);
|
||||
ASSERT_REG_POSITION(data_upload, 0x6D);
|
||||
ASSERT_REG_POSITION(sync_info, 0xB2);
|
||||
ASSERT_REG_POSITION(tfb_enabled, 0x1D1);
|
||||
ASSERT_REG_POSITION(rt, 0x200);
|
||||
|
|
|
|||
|
|
@ -83,57 +83,66 @@ void MaxwellDMA::HandleCopy() {
|
|||
|
||||
ASSERT(regs.exec.enable_2d == 1);
|
||||
|
||||
const std::size_t copy_size = regs.x_count * regs.y_count;
|
||||
|
||||
auto source_ptr{memory_manager.GetPointer(source)};
|
||||
auto dst_ptr{memory_manager.GetPointer(dest)};
|
||||
|
||||
if (!source_ptr) {
|
||||
LOG_ERROR(HW_GPU, "source_ptr is invalid");
|
||||
return;
|
||||
}
|
||||
|
||||
if (!dst_ptr) {
|
||||
LOG_ERROR(HW_GPU, "dst_ptr is invalid");
|
||||
return;
|
||||
}
|
||||
|
||||
const auto FlushAndInvalidate = [&](u32 src_size, u64 dst_size) {
|
||||
// TODO(Subv): For now, manually flush the regions until we implement GPU-accelerated
|
||||
// copying.
|
||||
rasterizer.FlushRegion(ToCacheAddr(source_ptr), src_size);
|
||||
|
||||
// We have to invalidate the destination region to evict any outdated surfaces from the
|
||||
// cache. We do this before actually writing the new data because the destination address
|
||||
// might contain a dirty surface that will have to be written back to memory.
|
||||
rasterizer.InvalidateRegion(ToCacheAddr(dst_ptr), dst_size);
|
||||
};
|
||||
|
||||
if (regs.exec.is_dst_linear && !regs.exec.is_src_linear) {
|
||||
ASSERT(regs.src_params.size_z == 1);
|
||||
// If the input is tiled and the output is linear, deswizzle the input and copy it over.
|
||||
|
||||
const u32 src_bytes_per_pixel = regs.src_pitch / regs.src_params.size_x;
|
||||
const std::size_t src_size = Texture::CalculateSize(
|
||||
true, src_bytes_per_pixel, regs.src_params.size_x, regs.src_params.size_y,
|
||||
regs.src_params.size_z, regs.src_params.BlockHeight(), regs.src_params.BlockDepth());
|
||||
|
||||
FlushAndInvalidate(regs.src_pitch * regs.src_params.size_y,
|
||||
copy_size * src_bytes_per_pixel);
|
||||
const std::size_t dst_size = regs.dst_pitch * regs.y_count;
|
||||
|
||||
if (read_buffer.size() < src_size) {
|
||||
read_buffer.resize(src_size);
|
||||
}
|
||||
|
||||
if (write_buffer.size() < dst_size) {
|
||||
write_buffer.resize(dst_size);
|
||||
}
|
||||
|
||||
memory_manager.ReadBlock(source, read_buffer.data(), src_size);
|
||||
memory_manager.ReadBlock(dest, write_buffer.data(), dst_size);
|
||||
|
||||
Texture::UnswizzleSubrect(regs.x_count, regs.y_count, regs.dst_pitch,
|
||||
regs.src_params.size_x, src_bytes_per_pixel, source_ptr, dst_ptr,
|
||||
regs.src_params.BlockHeight(), regs.src_params.pos_x,
|
||||
regs.src_params.pos_y);
|
||||
regs.src_params.size_x, src_bytes_per_pixel, read_buffer.data(),
|
||||
write_buffer.data(), regs.src_params.BlockHeight(),
|
||||
regs.src_params.pos_x, regs.src_params.pos_y);
|
||||
|
||||
memory_manager.WriteBlock(dest, write_buffer.data(), dst_size);
|
||||
} else {
|
||||
ASSERT(regs.dst_params.size_z == 1);
|
||||
ASSERT(regs.src_pitch == regs.x_count);
|
||||
ASSERT(regs.dst_params.BlockDepth() == 1);
|
||||
|
||||
const u32 src_bpp = regs.src_pitch / regs.x_count;
|
||||
const u32 src_bytes_per_pixel = regs.src_pitch / regs.x_count;
|
||||
|
||||
FlushAndInvalidate(regs.src_pitch * regs.y_count,
|
||||
regs.dst_params.size_x * regs.dst_params.size_y * src_bpp);
|
||||
const std::size_t dst_size = Texture::CalculateSize(
|
||||
true, src_bytes_per_pixel, regs.dst_params.size_x, regs.dst_params.size_y,
|
||||
regs.dst_params.size_z, regs.dst_params.BlockHeight(), regs.dst_params.BlockDepth());
|
||||
|
||||
const std::size_t dst_layer_size = Texture::CalculateSize(
|
||||
true, src_bytes_per_pixel, regs.dst_params.size_x, regs.dst_params.size_y, 1,
|
||||
regs.dst_params.BlockHeight(), regs.dst_params.BlockDepth());
|
||||
|
||||
const std::size_t src_size = regs.src_pitch * regs.y_count;
|
||||
|
||||
if (read_buffer.size() < src_size) {
|
||||
read_buffer.resize(src_size);
|
||||
}
|
||||
|
||||
if (write_buffer.size() < dst_size) {
|
||||
write_buffer.resize(dst_size);
|
||||
}
|
||||
|
||||
memory_manager.ReadBlock(source, read_buffer.data(), src_size);
|
||||
memory_manager.ReadBlock(dest, write_buffer.data(), dst_size);
|
||||
|
||||
// If the input is linear and the output is tiled, swizzle the input and copy it over.
|
||||
Texture::SwizzleSubrect(regs.x_count, regs.y_count, regs.src_pitch, regs.dst_params.size_x,
|
||||
src_bpp, dst_ptr, source_ptr, regs.dst_params.BlockHeight());
|
||||
src_bytes_per_pixel,
|
||||
write_buffer.data() + dst_layer_size * regs.dst_params.pos_z,
|
||||
read_buffer.data(), regs.dst_params.BlockHeight());
|
||||
|
||||
memory_manager.WriteBlock(dest, write_buffer.data(), dst_size);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@
|
|||
|
||||
#include <array>
|
||||
#include <cstddef>
|
||||
#include <vector>
|
||||
#include "common/bit_field.h"
|
||||
#include "common/common_funcs.h"
|
||||
#include "common/common_types.h"
|
||||
|
|
@ -25,6 +26,11 @@ class RasterizerInterface;
|
|||
|
||||
namespace Tegra::Engines {
|
||||
|
||||
/**
|
||||
* This Engine is known as GK104_Copy. Documentation can be found in:
|
||||
* https://github.com/envytools/envytools/blob/master/rnndb/fifo/gk104_copy.xml
|
||||
*/
|
||||
|
||||
class MaxwellDMA final {
|
||||
public:
|
||||
explicit MaxwellDMA(Core::System& system, VideoCore::RasterizerInterface& rasterizer,
|
||||
|
|
@ -63,6 +69,16 @@ public:
|
|||
|
||||
static_assert(sizeof(Parameters) == 24, "Parameters has wrong size");
|
||||
|
||||
enum class ComponentMode : u32 {
|
||||
Src0 = 0,
|
||||
Src1 = 1,
|
||||
Src2 = 2,
|
||||
Src3 = 3,
|
||||
Const0 = 4,
|
||||
Const1 = 5,
|
||||
Zero = 6,
|
||||
};
|
||||
|
||||
enum class CopyMode : u32 {
|
||||
None = 0,
|
||||
Unk1 = 1,
|
||||
|
|
@ -128,7 +144,26 @@ public:
|
|||
u32 x_count;
|
||||
u32 y_count;
|
||||
|
||||
INSERT_PADDING_WORDS(0xBB);
|
||||
INSERT_PADDING_WORDS(0xB8);
|
||||
|
||||
u32 const0;
|
||||
u32 const1;
|
||||
union {
|
||||
BitField<0, 4, ComponentMode> component0;
|
||||
BitField<4, 4, ComponentMode> component1;
|
||||
BitField<8, 4, ComponentMode> component2;
|
||||
BitField<12, 4, ComponentMode> component3;
|
||||
BitField<16, 2, u32> component_size;
|
||||
BitField<20, 3, u32> src_num_components;
|
||||
BitField<24, 3, u32> dst_num_components;
|
||||
|
||||
u32 SrcBytePerPixel() const {
|
||||
return src_num_components.Value() * component_size.Value();
|
||||
}
|
||||
u32 DstBytePerPixel() const {
|
||||
return dst_num_components.Value() * component_size.Value();
|
||||
}
|
||||
} swizzle_config;
|
||||
|
||||
Parameters dst_params;
|
||||
|
||||
|
|
@ -149,6 +184,9 @@ private:
|
|||
|
||||
MemoryManager& memory_manager;
|
||||
|
||||
std::vector<u8> read_buffer;
|
||||
std::vector<u8> write_buffer;
|
||||
|
||||
/// Performs the copy from the source buffer to the destination buffer as configured in the
|
||||
/// registers.
|
||||
void HandleCopy();
|
||||
|
|
@ -165,6 +203,9 @@ ASSERT_REG_POSITION(src_pitch, 0x104);
|
|||
ASSERT_REG_POSITION(dst_pitch, 0x105);
|
||||
ASSERT_REG_POSITION(x_count, 0x106);
|
||||
ASSERT_REG_POSITION(y_count, 0x107);
|
||||
ASSERT_REG_POSITION(const0, 0x1C0);
|
||||
ASSERT_REG_POSITION(const1, 0x1C1);
|
||||
ASSERT_REG_POSITION(swizzle_config, 0x1C2);
|
||||
ASSERT_REG_POSITION(dst_params, 0x1C3);
|
||||
ASSERT_REG_POSITION(src_params, 0x1CA);
|
||||
|
||||
|
|
|
|||
|
|
@ -35,9 +35,9 @@ GPU::GPU(Core::System& system, VideoCore::RendererBase& renderer) : renderer{ren
|
|||
dma_pusher = std::make_unique<Tegra::DmaPusher>(*this);
|
||||
maxwell_3d = std::make_unique<Engines::Maxwell3D>(system, rasterizer, *memory_manager);
|
||||
fermi_2d = std::make_unique<Engines::Fermi2D>(rasterizer, *memory_manager);
|
||||
kepler_compute = std::make_unique<Engines::KeplerCompute>(*memory_manager);
|
||||
kepler_compute = std::make_unique<Engines::KeplerCompute>(system, rasterizer, *memory_manager);
|
||||
maxwell_dma = std::make_unique<Engines::MaxwellDMA>(system, rasterizer, *memory_manager);
|
||||
kepler_memory = std::make_unique<Engines::KeplerMemory>(system, rasterizer, *memory_manager);
|
||||
kepler_memory = std::make_unique<Engines::KeplerMemory>(system, *memory_manager);
|
||||
}
|
||||
|
||||
GPU::~GPU() = default;
|
||||
|
|
|
|||
Loading…
Reference in a new issue