stuff/suyu
stuff/suyu
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/suyu.git synced 2024-11-29 23:06:23 -05:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

VideoCore/Shader: Extract DebugData out from UnitState

Browse source
This commit is contained in:
Yuri Kunde Schlesner 2016-12-15 23:57:10 -08:00
parent 6e7e767645
commit c135317de1
8 changed files with 99 additions and 103 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/video_core/command_processor.cpp
View file

@ -138,7 +138,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
if (immediate_attribute_id >= regs.vs.num_input_attributes + 1) { if (immediate_attribute_id >= regs.vs.num_input_attributes + 1) {
immediate_attribute_id = 0; immediate_attribute_id = 0;
Shader::UnitState<false> shader_unit; Shader::UnitState shader_unit;
g_state.vs.Setup(); g_state.vs.Setup();
// Send to vertex shader // Send to vertex shader
@ -237,7 +237,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
unsigned int vertex_cache_pos = 0; unsigned int vertex_cache_pos = 0;
vertex_cache_ids.fill(-1); vertex_cache_ids.fill(-1);
Shader::UnitState<false> shader_unit; Shader::UnitState shader_unit;
g_state.vs.Setup(); g_state.vs.Setup();
for (unsigned int index = 0; index < regs.num_vertices; ++index) { for (unsigned int index = 0; index < regs.num_vertices; ++index) {

8
src/video_core/shader/debug_data.h
View file

@ -19,8 +19,8 @@ struct DebugData;
template <> template <>
struct DebugData<false> { struct DebugData<false> {
// TODO: Hide these behind and interface and move them to DebugData<true> // TODO: Hide these behind and interface and move them to DebugData<true>
u32 max_offset; ///< maximum program counter ever reached u32 max_offset = 0; ///< maximum program counter ever reached
u32 max_opdesc_id; ///< maximum swizzle pattern index ever used u32 max_opdesc_id = 0; ///< maximum swizzle pattern index ever used
}; };
template <> template <>
@ -75,8 +75,8 @@ struct DebugData<true> {
unsigned mask = 0; unsigned mask = 0;
}; };
u32 max_offset; ///< maximum program counter ever reached u32 max_offset = 0; ///< maximum program counter ever reached
u32 max_opdesc_id; ///< maximum swizzle pattern index ever used u32 max_opdesc_id = 0; ///< maximum swizzle pattern index ever used
/// List of records for each executed shader instruction /// List of records for each executed shader instruction
std::vector<DebugData<true>::Record> records; std::vector<DebugData<true>::Record> records;

26
src/video_core/shader/shader.cpp
View file

@ -109,15 +109,12 @@ void ShaderSetup::Setup() {
MICROPROFILE_DEFINE(GPU_Shader, "GPU", "Shader", MP_RGB(50, 50, 240)); MICROPROFILE_DEFINE(GPU_Shader, "GPU", "Shader", MP_RGB(50, 50, 240));
void ShaderSetup::Run(UnitState<false>& state, const InputVertex& input, int num_attributes) { void ShaderSetup::Run(UnitState& state, const InputVertex& input, int num_attributes) {
auto& config = g_state.regs.vs; auto& config = g_state.regs.vs;
auto& setup = g_state.vs; auto& setup = g_state.vs;
MICROPROFILE_SCOPE(GPU_Shader); MICROPROFILE_SCOPE(GPU_Shader);
state.debug.max_offset = 0;
state.debug.max_opdesc_id = 0;
// Setup input register table // Setup input register table
const auto& attribute_register_map = config.input_register_map; const auto& attribute_register_map = config.input_register_map;
@ -128,22 +125,23 @@ void ShaderSetup::Run(UnitState<false>& state, const InputVertex& input, int num
state.conditional_code[1] = false; state.conditional_code[1] = false;
#ifdef ARCHITECTURE_x86_64 #ifdef ARCHITECTURE_x86_64
if (VideoCore::g_shader_jit_enabled) if (VideoCore::g_shader_jit_enabled) {
jit_shader->Run(setup, state, config.main_offset); jit_shader->Run(setup, state, config.main_offset);
else } else {
RunInterpreter(setup, state, config.main_offset); DebugData<false> dummy_debug_data;
RunInterpreter(setup, state, dummy_debug_data, config.main_offset);
}
#else #else
RunInterpreter(setup, state, config.main_offset); DebugData<false> dummy_debug_data;
RunInterpreter(setup, state, dummy_debug_data, config.main_offset);
#endif // ARCHITECTURE_x86_64 #endif // ARCHITECTURE_x86_64
} }
DebugData<true> ShaderSetup::ProduceDebugInfo(const InputVertex& input, int num_attributes, DebugData<true> ShaderSetup::ProduceDebugInfo(const InputVertex& input, int num_attributes,
const Regs::ShaderConfig& config, const Regs::ShaderConfig& config,
const ShaderSetup& setup) { const ShaderSetup& setup) {
UnitState<true> state; UnitState state;
DebugData<true> debug_data;
state.debug.max_offset = 0;
state.debug.max_opdesc_id = 0;
// Setup input register table // Setup input register table
boost::fill(state.registers.input, Math::Vec4<float24>::AssignToAll(float24::Zero())); boost::fill(state.registers.input, Math::Vec4<float24>::AssignToAll(float24::Zero()));
@ -154,8 +152,8 @@ DebugData<true> ShaderSetup::ProduceDebugInfo(const InputVertex& input, int num_
state.conditional_code[0] = false; state.conditional_code[0] = false;
state.conditional_code[1] = false; state.conditional_code[1] = false;
RunInterpreter(setup, state, config.main_offset); RunInterpreter(setup, state, debug_data, config.main_offset);
return state.debug; return debug_data;
} }
} // namespace Shader } // namespace Shader

5
src/video_core/shader/shader.h
View file

@ -94,7 +94,6 @@ static_assert(std::is_pod<OutputRegisters>::value, "Structure is not POD");
* single shader unit that processes all shaders serially. Putting the state information in a struct * single shader unit that processes all shaders serially. Putting the state information in a struct
* here will make it easier for us to parallelize the shader processing later. * here will make it easier for us to parallelize the shader processing later.
*/ */
template <bool Debug>
struct UnitState { struct UnitState {
struct Registers { struct Registers {
// The registers are accessed by the shader JIT using SSE instructions, and are therefore // The registers are accessed by the shader JIT using SSE instructions, and are therefore
@ -112,8 +111,6 @@ struct UnitState {
// TODO: How many bits do these actually have? // TODO: How many bits do these actually have?
s32 address_registers[3]; s32 address_registers[3];
DebugData<Debug> debug;
static size_t InputOffset(const SourceRegister& reg) { static size_t InputOffset(const SourceRegister& reg) {
switch (reg.GetRegisterType()) { switch (reg.GetRegisterType()) {
case RegisterType::Input: case RegisterType::Input:
@ -188,7 +185,7 @@ struct ShaderSetup {
* @param input Input vertex into the shader * @param input Input vertex into the shader
* @param num_attributes The number of vertex shader attributes * @param num_attributes The number of vertex shader attributes
*/ */
void Run(UnitState<false>& state, const InputVertex& input, int num_attributes); void Run(UnitState& state, const InputVertex& input, int num_attributes);
/** /**
* Produce debug information based on the given shader and input vertex * Produce debug information based on the given shader and input vertex

146
src/video_core/shader/shader_interpreter.cpp
View file

@ -39,7 +39,8 @@ struct CallStackElement {
}; };
template <bool Debug> template <bool Debug>
void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned offset) { void RunInterpreter(const ShaderSetup& setup, UnitState& state, DebugData<Debug>& debug_data,
unsigned offset) {
// TODO: Is there a maximal size for this? // TODO: Is there a maximal size for this?
boost::container::static_vector<CallStackElement, 16> call_stack; boost::container::static_vector<CallStackElement, 16> call_stack;
u32 program_counter = offset; u32 program_counter = offset;
@ -104,11 +105,11 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
const Instruction instr = {program_code[program_counter]}; const Instruction instr = {program_code[program_counter]};
const SwizzlePattern swizzle = {swizzle_data[instr.common.operand_desc_id]}; const SwizzlePattern swizzle = {swizzle_data[instr.common.operand_desc_id]};
Record<DebugDataRecord::CUR_INSTR>(state.debug, iteration, program_counter); Record<DebugDataRecord::CUR_INSTR>(debug_data, iteration, program_counter);
if (iteration > 0) if (iteration > 0)
Record<DebugDataRecord::NEXT_INSTR>(state.debug, iteration - 1, program_counter); Record<DebugDataRecord::NEXT_INSTR>(debug_data, iteration - 1, program_counter);
state.debug.max_offset = std::max<u32>(state.debug.max_offset, 1 + program_counter); debug_data.max_offset = std::max<u32>(debug_data.max_offset, 1 + program_counter);
auto LookupSourceRegister = [&](const SourceRegister& source_reg) -> const float24* { auto LookupSourceRegister = [&](const SourceRegister& source_reg) -> const float24* {
switch (source_reg.GetRegisterType()) { switch (source_reg.GetRegisterType()) {
@ -176,54 +177,54 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
? &state.registers.temporary[instr.common.dest.Value().GetIndex()][0] ? &state.registers.temporary[instr.common.dest.Value().GetIndex()][0]
: dummy_vec4_float24; : dummy_vec4_float24;
state.debug.max_opdesc_id = debug_data.max_opdesc_id =
std::max<u32>(state.debug.max_opdesc_id, 1 + instr.common.operand_desc_id); std::max<u32>(debug_data.max_opdesc_id, 1 + instr.common.operand_desc_id);
switch (instr.opcode.Value().EffectiveOpCode()) { switch (instr.opcode.Value().EffectiveOpCode()) {
case OpCode::Id::ADD: { case OpCode::Id::ADD: {
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1); Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2); Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
for (int i = 0; i < 4; ++i) { for (int i = 0; i < 4; ++i) {
if (!swizzle.DestComponentEnabled(i)) if (!swizzle.DestComponentEnabled(i))
continue; continue;
dest[i] = src1[i] + src2[i]; dest[i] = src1[i] + src2[i];
} }
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
break; break;
} }
case OpCode::Id::MUL: { case OpCode::Id::MUL: {
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1); Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2); Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
for (int i = 0; i < 4; ++i) { for (int i = 0; i < 4; ++i) {
if (!swizzle.DestComponentEnabled(i)) if (!swizzle.DestComponentEnabled(i))
continue; continue;
dest[i] = src1[i] * src2[i]; dest[i] = src1[i] * src2[i];
} }
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
break; break;
} }
case OpCode::Id::FLR: case OpCode::Id::FLR:
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1); Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
for (int i = 0; i < 4; ++i) { for (int i = 0; i < 4; ++i) {
if (!swizzle.DestComponentEnabled(i)) if (!swizzle.DestComponentEnabled(i))
continue; continue;
dest[i] = float24::FromFloat32(std::floor(src1[i].ToFloat32())); dest[i] = float24::FromFloat32(std::floor(src1[i].ToFloat32()));
} }
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
break; break;
case OpCode::Id::MAX: case OpCode::Id::MAX:
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1); Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2); Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
for (int i = 0; i < 4; ++i) { for (int i = 0; i < 4; ++i) {
if (!swizzle.DestComponentEnabled(i)) if (!swizzle.DestComponentEnabled(i))
continue; continue;
@ -233,13 +234,13 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
// max(NaN, 0) -> 0 // max(NaN, 0) -> 0
dest[i] = (src1[i] > src2[i]) ? src1[i] : src2[i]; dest[i] = (src1[i] > src2[i]) ? src1[i] : src2[i];
} }
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
break; break;
case OpCode::Id::MIN: case OpCode::Id::MIN:
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1); Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2); Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
for (int i = 0; i < 4; ++i) { for (int i = 0; i < 4; ++i) {
if (!swizzle.DestComponentEnabled(i)) if (!swizzle.DestComponentEnabled(i))
continue; continue;
@ -249,16 +250,16 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
// min(NaN, 0) -> 0 // min(NaN, 0) -> 0
dest[i] = (src1[i] < src2[i]) ? src1[i] : src2[i]; dest[i] = (src1[i] < src2[i]) ? src1[i] : src2[i];
} }
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
break; break;
case OpCode::Id::DP3: case OpCode::Id::DP3:
case OpCode::Id::DP4: case OpCode::Id::DP4:
case OpCode::Id::DPH: case OpCode::Id::DPH:
case OpCode::Id::DPHI: { case OpCode::Id::DPHI: {
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1); Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2); Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
OpCode::Id opcode = instr.opcode.Value().EffectiveOpCode(); OpCode::Id opcode = instr.opcode.Value().EffectiveOpCode();
if (opcode == OpCode::Id::DPH || opcode == OpCode::Id::DPHI) if (opcode == OpCode::Id::DPH || opcode == OpCode::Id::DPHI)
@ -274,14 +275,14 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
dest[i] = dot; dest[i] = dot;
} }
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
break; break;
} }
// Reciprocal // Reciprocal
case OpCode::Id::RCP: { case OpCode::Id::RCP: {
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1); Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
float24 rcp_res = float24::FromFloat32(1.0f / src1[0].ToFloat32()); float24 rcp_res = float24::FromFloat32(1.0f / src1[0].ToFloat32());
for (int i = 0; i < 4; ++i) { for (int i = 0; i < 4; ++i) {
if (!swizzle.DestComponentEnabled(i)) if (!swizzle.DestComponentEnabled(i))
@ -289,14 +290,14 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
dest[i] = rcp_res; dest[i] = rcp_res;
} }
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
break; break;
} }
// Reciprocal Square Root // Reciprocal Square Root
case OpCode::Id::RSQ: { case OpCode::Id::RSQ: {
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1); Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
float24 rsq_res = float24::FromFloat32(1.0f / std::sqrt(src1[0].ToFloat32())); float24 rsq_res = float24::FromFloat32(1.0f / std::sqrt(src1[0].ToFloat32()));
for (int i = 0; i < 4; ++i) { for (int i = 0; i < 4; ++i) {
if (!swizzle.DestComponentEnabled(i)) if (!swizzle.DestComponentEnabled(i))
@ -304,12 +305,12 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
dest[i] = rsq_res; dest[i] = rsq_res;
} }
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
break; break;
} }
case OpCode::Id::MOVA: { case OpCode::Id::MOVA: {
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1); Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
for (int i = 0; i < 2; ++i) { for (int i = 0; i < 2; ++i) {
if (!swizzle.DestComponentEnabled(i)) if (!swizzle.DestComponentEnabled(i))
continue; continue;
@ -317,29 +318,29 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
// TODO: Figure out how the rounding is done on hardware // TODO: Figure out how the rounding is done on hardware
state.address_registers[i] = static_cast<s32>(src1[i].ToFloat32()); state.address_registers[i] = static_cast<s32>(src1[i].ToFloat32());
} }
Record<DebugDataRecord::ADDR_REG_OUT>(state.debug, iteration, Record<DebugDataRecord::ADDR_REG_OUT>(debug_data, iteration,
state.address_registers); state.address_registers);
break; break;
} }
case OpCode::Id::MOV: { case OpCode::Id::MOV: {
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1); Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
for (int i = 0; i < 4; ++i) { for (int i = 0; i < 4; ++i) {
if (!swizzle.DestComponentEnabled(i)) if (!swizzle.DestComponentEnabled(i))
continue; continue;
dest[i] = src1[i]; dest[i] = src1[i];
} }
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
break; break;
} }
case OpCode::Id::SGE: case OpCode::Id::SGE:
case OpCode::Id::SGEI: case OpCode::Id::SGEI:
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1); Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2); Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
for (int i = 0; i < 4; ++i) { for (int i = 0; i < 4; ++i) {
if (!swizzle.DestComponentEnabled(i)) if (!swizzle.DestComponentEnabled(i))
continue; continue;
@ -347,14 +348,14 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
dest[i] = (src1[i] >= src2[i]) ? float24::FromFloat32(1.0f) dest[i] = (src1[i] >= src2[i]) ? float24::FromFloat32(1.0f)
: float24::FromFloat32(0.0f); : float24::FromFloat32(0.0f);
} }
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
break; break;
case OpCode::Id::SLT: case OpCode::Id::SLT:
case OpCode::Id::SLTI: case OpCode::Id::SLTI:
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1); Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2); Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
for (int i = 0; i < 4; ++i) { for (int i = 0; i < 4; ++i) {
if (!swizzle.DestComponentEnabled(i)) if (!swizzle.DestComponentEnabled(i))
continue; continue;
@ -362,12 +363,12 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
dest[i] = (src1[i] < src2[i]) ? float24::FromFloat32(1.0f) dest[i] = (src1[i] < src2[i]) ? float24::FromFloat32(1.0f)
: float24::FromFloat32(0.0f); : float24::FromFloat32(0.0f);
} }
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
break; break;
case OpCode::Id::CMP: case OpCode::Id::CMP:
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1); Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2); Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
for (int i = 0; i < 2; ++i) { for (int i = 0; i < 2; ++i) {
// TODO: Can you restrict to one compare via dest masking? // TODO: Can you restrict to one compare via dest masking?
@ -404,12 +405,12 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
break; break;
} }
} }
Record<DebugDataRecord::CMP_RESULT>(state.debug, iteration, state.conditional_code); Record<DebugDataRecord::CMP_RESULT>(debug_data, iteration, state.conditional_code);
break; break;
case OpCode::Id::EX2: { case OpCode::Id::EX2: {
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1); Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
// EX2 only takes first component exp2 and writes it to all dest components // EX2 only takes first component exp2 and writes it to all dest components
float24 ex2_res = float24::FromFloat32(std::exp2(src1[0].ToFloat32())); float24 ex2_res = float24::FromFloat32(std::exp2(src1[0].ToFloat32()));
@ -420,13 +421,13 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
dest[i] = ex2_res; dest[i] = ex2_res;
} }
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
break; break;
} }
case OpCode::Id::LG2: { case OpCode::Id::LG2: {
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1); Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
// LG2 only takes the first component log2 and writes it to all dest components // LG2 only takes the first component log2 and writes it to all dest components
float24 lg2_res = float24::FromFloat32(std::log2(src1[0].ToFloat32())); float24 lg2_res = float24::FromFloat32(std::log2(src1[0].ToFloat32()));
@ -437,7 +438,7 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
dest[i] = lg2_res; dest[i] = lg2_res;
} }
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
break; break;
} }
@ -519,17 +520,17 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
? &state.registers.temporary[instr.mad.dest.Value().GetIndex()][0] ? &state.registers.temporary[instr.mad.dest.Value().GetIndex()][0]
: dummy_vec4_float24; : dummy_vec4_float24;
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1); Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2); Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
Record<DebugDataRecord::SRC3>(state.debug, iteration, src3); Record<DebugDataRecord::SRC3>(debug_data, iteration, src3);
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
for (int i = 0; i < 4; ++i) { for (int i = 0; i < 4; ++i) {
if (!swizzle.DestComponentEnabled(i)) if (!swizzle.DestComponentEnabled(i))
continue; continue;
dest[i] = src1[i] * src2[i] + src3[i]; dest[i] = src1[i] * src2[i] + src3[i];
} }
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest); Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
} else { } else {
LOG_ERROR(HW_GPU, "Unhandled multiply-add instruction: 0x%02x (%s): 0x%08x", LOG_ERROR(HW_GPU, "Unhandled multiply-add instruction: 0x%02x (%s): 0x%08x",
(int)instr.opcode.Value().EffectiveOpCode(), (int)instr.opcode.Value().EffectiveOpCode(),
@ -546,8 +547,7 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
break; break;
case OpCode::Id::JMPC: case OpCode::Id::JMPC:
Record<DebugDataRecord::COND_CMP_IN>(state.debug, iteration, Record<DebugDataRecord::COND_CMP_IN>(debug_data, iteration, state.conditional_code);
state.conditional_code);
if (evaluate_condition(instr.flow_control)) { if (evaluate_condition(instr.flow_control)) {
program_counter = instr.flow_control.dest_offset - 1; program_counter = instr.flow_control.dest_offset - 1;
} }
@ -555,7 +555,7 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
case OpCode::Id::JMPU: case OpCode::Id::JMPU:
Record<DebugDataRecord::COND_BOOL_IN>( Record<DebugDataRecord::COND_BOOL_IN>(
state.debug, iteration, uniforms.b[instr.flow_control.bool_uniform_id]); debug_data, iteration, uniforms.b[instr.flow_control.bool_uniform_id]);
if (uniforms.b[instr.flow_control.bool_uniform_id] == if (uniforms.b[instr.flow_control.bool_uniform_id] ==
!(instr.flow_control.num_instructions & 1)) { !(instr.flow_control.num_instructions & 1)) {
@ -570,7 +570,7 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
case OpCode::Id::CALLU: case OpCode::Id::CALLU:
Record<DebugDataRecord::COND_BOOL_IN>( Record<DebugDataRecord::COND_BOOL_IN>(
state.debug, iteration, uniforms.b[instr.flow_control.bool_uniform_id]); debug_data, iteration, uniforms.b[instr.flow_control.bool_uniform_id]);
if (uniforms.b[instr.flow_control.bool_uniform_id]) { if (uniforms.b[instr.flow_control.bool_uniform_id]) {
call(instr.flow_control.dest_offset, instr.flow_control.num_instructions, call(instr.flow_control.dest_offset, instr.flow_control.num_instructions,
program_counter + 1, 0, 0); program_counter + 1, 0, 0);
@ -578,8 +578,7 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
break; break;
case OpCode::Id::CALLC: case OpCode::Id::CALLC:
Record<DebugDataRecord::COND_CMP_IN>(state.debug, iteration, Record<DebugDataRecord::COND_CMP_IN>(debug_data, iteration, state.conditional_code);
state.conditional_code);
if (evaluate_condition(instr.flow_control)) { if (evaluate_condition(instr.flow_control)) {
call(instr.flow_control.dest_offset, instr.flow_control.num_instructions, call(instr.flow_control.dest_offset, instr.flow_control.num_instructions,
program_counter + 1, 0, 0); program_counter + 1, 0, 0);
@ -591,7 +590,7 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
case OpCode::Id::IFU: case OpCode::Id::IFU:
Record<DebugDataRecord::COND_BOOL_IN>( Record<DebugDataRecord::COND_BOOL_IN>(
state.debug, iteration, uniforms.b[instr.flow_control.bool_uniform_id]); debug_data, iteration, uniforms.b[instr.flow_control.bool_uniform_id]);
if (uniforms.b[instr.flow_control.bool_uniform_id]) { if (uniforms.b[instr.flow_control.bool_uniform_id]) {
call(program_counter + 1, instr.flow_control.dest_offset - program_counter - 1, call(program_counter + 1, instr.flow_control.dest_offset - program_counter - 1,
instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0, instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0,
@ -607,8 +606,7 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
case OpCode::Id::IFC: { case OpCode::Id::IFC: {
// TODO: Do we need to consider swizzlers here? // TODO: Do we need to consider swizzlers here?
Record<DebugDataRecord::COND_CMP_IN>(state.debug, iteration, Record<DebugDataRecord::COND_CMP_IN>(debug_data, iteration, state.conditional_code);
state.conditional_code);
if (evaluate_condition(instr.flow_control)) { if (evaluate_condition(instr.flow_control)) {
call(program_counter + 1, instr.flow_control.dest_offset - program_counter - 1, call(program_counter + 1, instr.flow_control.dest_offset - program_counter - 1,
instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0, instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0,
@ -629,7 +627,7 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
uniforms.i[instr.flow_control.int_uniform_id].w); uniforms.i[instr.flow_control.int_uniform_id].w);
state.address_registers[2] = loop_param.y; state.address_registers[2] = loop_param.y;
Record<DebugDataRecord::LOOP_INT_IN>(state.debug, iteration, loop_param); Record<DebugDataRecord::LOOP_INT_IN>(debug_data, iteration, loop_param);
call(program_counter + 1, instr.flow_control.dest_offset - program_counter + 1, call(program_counter + 1, instr.flow_control.dest_offset - program_counter + 1,
instr.flow_control.dest_offset + 1, loop_param.x, loop_param.z); instr.flow_control.dest_offset + 1, loop_param.x, loop_param.z);
break; break;
@ -652,8 +650,8 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
} }
// Explicit instantiation // Explicit instantiation
template void RunInterpreter(const ShaderSetup& setup, UnitState<false>& state, unsigned offset); template void RunInterpreter(const ShaderSetup&, UnitState&, DebugData<false>&, unsigned offset);
template void RunInterpreter(const ShaderSetup& setup, UnitState<true>& state, unsigned offset); template void RunInterpreter(const ShaderSetup&, UnitState&, DebugData<true>&, unsigned offset);
} // namespace } // namespace

7
src/video_core/shader/shader_interpreter.h
View file

@ -8,11 +8,14 @@ namespace Pica {
namespace Shader { namespace Shader {
template <bool Debug>
struct UnitState; struct UnitState;
template <bool Debug> template <bool Debug>
void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned offset); struct DebugData;
template <bool Debug>
void RunInterpreter(const ShaderSetup& setup, UnitState& state, DebugData<Debug>& debug_data,
unsigned offset);
} // namespace } // namespace

4
src/video_core/shader/shader_jit_x64.cpp
View file

@ -188,7 +188,7 @@ void JitShader::Compile_SwizzleSrc(Instruction instr, unsigned src_num, SourceRe
src_offset = ShaderSetup::GetFloatUniformOffset(src_reg.GetIndex()); src_offset = ShaderSetup::GetFloatUniformOffset(src_reg.GetIndex());
} else { } else {
src_ptr = STATE; src_ptr = STATE;
src_offset = UnitState<false>::InputOffset(src_reg); src_offset = UnitState::InputOffset(src_reg);
} }
int src_offset_disp = (int)src_offset; int src_offset_disp = (int)src_offset;
@ -266,7 +266,7 @@ void JitShader::Compile_DestEnable(Instruction instr, Xmm src) {
SwizzlePattern swiz = {g_state.vs.swizzle_data[operand_desc_id]}; SwizzlePattern swiz = {g_state.vs.swizzle_data[operand_desc_id]};
size_t dest_offset_disp = UnitState<false>::OutputOffset(dest); size_t dest_offset_disp = UnitState::OutputOffset(dest);
// If all components are enabled, write the result to the destination register // If all components are enabled, write the result to the destination register
if (swiz.dest_mask == NO_DEST_REG_MASK) { if (swiz.dest_mask == NO_DEST_REG_MASK) {

2
src/video_core/shader/shader_jit_x64.h
View file

@ -34,7 +34,7 @@ class JitShader : public Xbyak::CodeGenerator {
public: public:
JitShader(); JitShader();
void Run(const ShaderSetup& setup, UnitState<false>& state, unsigned offset) const { void Run(const ShaderSetup& setup, UnitState& state, unsigned offset) const {
program(&setup, &state, instruction_labels[offset].getAddress()); program(&setup, &state, instruction_labels[offset].getAddress());
} }