stuff/suyu
stuff/suyu
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/suyu.git synced 2024-11-29 23:06:23 -05:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

Correct CNTPCT to use Clock Cycles instead of Cpu Cycles.

Browse source
This commit is contained in:
Fernando Sahmkow 2019-02-15 13:15:28 -04:00 committed by FernandoS27
parent 99da6362c4
commit 5b7ec71fb7
3 changed files with 13 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
src/core/arm/dynarmic/arm_dynarmic.cpp
View file

@ -12,6 +12,7 @@
#include "core/core.h" #include "core/core.h"
#include "core/core_cpu.h" #include "core/core_cpu.h"
#include "core/core_timing.h" #include "core/core_timing.h"
#include "core/core_timing_util.h"
#include "core/gdbstub/gdbstub.h" #include "core/gdbstub/gdbstub.h"
#include "core/hle/kernel/process.h" #include "core/hle/kernel/process.h"
#include "core/hle/kernel/svc.h" #include "core/hle/kernel/svc.h"
@ -119,7 +120,7 @@ public:
return std::max(parent.core_timing.GetDowncount(), 0); return std::max(parent.core_timing.GetDowncount(), 0);
} }
u64 GetCNTPCT() override { u64 GetCNTPCT() override {
return parent.core_timing.GetTicks(); return CpuCyclesToClockCycles(parent.core_timing.GetTicks());
} }
ARM_Dynarmic& parent; ARM_Dynarmic& parent;
@ -151,7 +152,7 @@ std::unique_ptr<Dynarmic::A64::Jit> ARM_Dynarmic::MakeJit() const {
config.tpidr_el0 = &cb->tpidr_el0; config.tpidr_el0 = &cb->tpidr_el0;
config.dczid_el0 = 4; config.dczid_el0 = 4;
config.ctr_el0 = 0x8444c004; config.ctr_el0 = 0x8444c004;
config.cntfrq_el0 = 19200000; // Value from fusee. config.cntfrq_el0 = Timing::CNTFREQ; // Value from fusee.
// Unpredictable instructions // Unpredictable instructions
config.define_unpredictable_behaviour = true; config.define_unpredictable_behaviour = true;

7
src/core/core_timing_util.cpp
View file

@ -60,4 +60,11 @@ s64 nsToCycles(u64 ns) {
return (BASE_CLOCK_RATE * static_cast<s64>(ns)) / 1000000000; return (BASE_CLOCK_RATE * static_cast<s64>(ns)) / 1000000000;
} }
u64 CpuCyclesToClockCycles(u64 ticks) {
u64 result = ticks;
result *= CNTFREQ;
result /= BASE_CLOCK_RATE;
return static_cast<u64>(result);
}
} // namespace Core::Timing } // namespace Core::Timing

3
src/core/core_timing_util.h
View file

@ -11,6 +11,7 @@ namespace Core::Timing {
// The below clock rate is based on Switch's clockspeed being widely known as 1.020GHz // The below clock rate is based on Switch's clockspeed being widely known as 1.020GHz
// The exact value used is of course unverified. // The exact value used is of course unverified.
constexpr u64 BASE_CLOCK_RATE = 1019215872; // Switch clock speed is 1020MHz un/docked constexpr u64 BASE_CLOCK_RATE = 1019215872; // Switch clock speed is 1020MHz un/docked
constexpr u64 CNTFREQ = 19200000; // Value from fusee.
inline s64 msToCycles(int ms) { inline s64 msToCycles(int ms) {
// since ms is int there is no way to overflow // since ms is int there is no way to overflow
@ -61,4 +62,6 @@ inline u64 cyclesToMs(s64 cycles) {
return cycles * 1000 / BASE_CLOCK_RATE; return cycles * 1000 / BASE_CLOCK_RATE;
} }
u64 CpuCyclesToClockCycles(u64 ticks);
} // namespace Core::Timing } // namespace Core::Timing