mirror of
https://git.suyu.dev/suyu/suyu.git
synced 2024-11-29 14:57:41 -05:00
Merge branch 'master' into threading
This commit is contained in:
commit
3fac6dc39e
8 changed files with 44 additions and 30 deletions
|
@ -33,9 +33,7 @@ int __cdecl main(int argc, char **argv) {
|
||||||
ERROR_LOG(BOOT, "Failed to load ROM: %s", error_str.c_str());
|
ERROR_LOG(BOOT, "Failed to load ROM: %s", error_str.c_str());
|
||||||
}
|
}
|
||||||
|
|
||||||
for (;;) {
|
Core::RunLoop();
|
||||||
Core::SingleStep();
|
|
||||||
}
|
|
||||||
|
|
||||||
delete emu_window;
|
delete emu_window;
|
||||||
|
|
||||||
|
|
|
@ -6,6 +6,8 @@
|
||||||
|
|
||||||
#include "core/core.h"
|
#include "core/core.h"
|
||||||
#include "core/loader.h"
|
#include "core/loader.h"
|
||||||
|
#include "core/hw/hw.h"
|
||||||
|
|
||||||
#include "video_core/video_core.h"
|
#include "video_core/video_core.h"
|
||||||
|
|
||||||
#include "version.h"
|
#include "version.h"
|
||||||
|
@ -40,6 +42,7 @@ void EmuThread::run()
|
||||||
emit CPUStepped();
|
emit CPUStepped();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
HW::Update();
|
||||||
}
|
}
|
||||||
|
|
||||||
Core::Stop();
|
Core::Stop();
|
||||||
|
|
|
@ -17,10 +17,18 @@ public:
|
||||||
~ARM_Interface() {
|
~ARM_Interface() {
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Runs the CPU for the given number of instructions
|
||||||
|
* @param num_instructions Number of instructions to run
|
||||||
|
*/
|
||||||
|
void Run(int num_instructions) {
|
||||||
|
ExecuteInstructions(num_instructions);
|
||||||
|
m_num_instructions += num_instructions;
|
||||||
|
}
|
||||||
|
|
||||||
/// Step CPU by one instruction
|
/// Step CPU by one instruction
|
||||||
void Step() {
|
void Step() {
|
||||||
ExecuteInstruction();
|
Run(1);
|
||||||
m_num_instructions++;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -74,8 +82,11 @@ public:
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
|
|
||||||
/// Execture next instruction
|
/**
|
||||||
virtual void ExecuteInstruction() = 0;
|
* Executes the given number of instructions
|
||||||
|
* @param num_instructions Number of instructions to executes
|
||||||
|
*/
|
||||||
|
virtual void ExecuteInstructions(int num_instructions) = 0;
|
||||||
|
|
||||||
private:
|
private:
|
||||||
|
|
||||||
|
|
|
@ -93,16 +93,11 @@ u64 ARM_Interpreter::GetTicks() const {
|
||||||
return ARMul_Time(m_state);
|
return ARMul_Time(m_state);
|
||||||
}
|
}
|
||||||
|
|
||||||
/// Execture next instruction
|
/**
|
||||||
void ARM_Interpreter::ExecuteInstruction() {
|
* Executes the given number of instructions
|
||||||
m_state->step++;
|
* @param num_instructions Number of instructions to executes
|
||||||
m_state->cycle++;
|
*/
|
||||||
m_state->EndCondition = 0;
|
void ARM_Interpreter::ExecuteInstructions(int num_instructions) {
|
||||||
m_state->stop_simulator = 0;
|
m_state->NumInstrsToExecute = num_instructions;
|
||||||
m_state->NextInstr = RESUME;
|
ARMul_Emulate32(m_state);
|
||||||
m_state->last_pc = m_state->Reg[15];
|
|
||||||
m_state->Reg[15] = ARMul_DoInstr(m_state);
|
|
||||||
m_state->Cpsr = ((m_state->Cpsr & 0x0fffffdf) | (m_state->NFlag << 31) | (m_state->ZFlag << 30) |
|
|
||||||
(m_state->CFlag << 29) | (m_state->VFlag << 28) | (m_state->TFlag << 5));
|
|
||||||
m_state->NextInstr |= PRIMEPIPE; // Flush pipe
|
|
||||||
}
|
}
|
||||||
|
|
|
@ -62,8 +62,11 @@ public:
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
|
|
||||||
/// Execture next instruction
|
/**
|
||||||
void ExecuteInstruction();
|
* Executes the given number of instructions
|
||||||
|
* @param num_instructions Number of instructions to executes
|
||||||
|
*/
|
||||||
|
void ExecuteInstructions(int num_instructions);
|
||||||
|
|
||||||
private:
|
private:
|
||||||
|
|
||||||
|
|
|
@ -288,6 +288,7 @@ struct ARMul_State
|
||||||
ARMword loaded_addr, decoded_addr; /* saved pipeline state addr*/
|
ARMword loaded_addr, decoded_addr; /* saved pipeline state addr*/
|
||||||
unsigned int NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles; /* emulated cycles used */
|
unsigned int NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles; /* emulated cycles used */
|
||||||
unsigned long long NumInstrs; /* the number of instructions executed */
|
unsigned long long NumInstrs; /* the number of instructions executed */
|
||||||
|
unsigned NumInstrsToExecute;
|
||||||
unsigned NextInstr;
|
unsigned NextInstr;
|
||||||
unsigned VectorCatch; /* caught exception mask */
|
unsigned VectorCatch; /* caught exception mask */
|
||||||
unsigned CallDebug; /* set to call the debugger */
|
unsigned CallDebug; /* set to call the debugger */
|
||||||
|
|
|
@ -4734,7 +4734,7 @@ TEST_EMULATE:
|
||||||
else if (state->Emulate != RUN)
|
else if (state->Emulate != RUN)
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
while (!state->stop_simulator);
|
while (state->NumInstrsToExecute--);
|
||||||
|
|
||||||
state->decoded = decoded;
|
state->decoded = decoded;
|
||||||
state->loaded = loaded;
|
state->loaded = loaded;
|
||||||
|
|
|
@ -4,8 +4,9 @@
|
||||||
|
|
||||||
#include "common/common_types.h"
|
#include "common/common_types.h"
|
||||||
#include "common/log.h"
|
#include "common/log.h"
|
||||||
#include "core/core.h"
|
#include "common/symbols.h"
|
||||||
|
|
||||||
|
#include "core/core.h"
|
||||||
#include "core/mem_map.h"
|
#include "core/mem_map.h"
|
||||||
#include "core/hw/hw.h"
|
#include "core/hw/hw.h"
|
||||||
#include "core/arm/disassembler/arm_disasm.h"
|
#include "core/arm/disassembler/arm_disasm.h"
|
||||||
|
@ -19,13 +20,15 @@ ARM_Interface* g_sys_core = NULL; ///< ARM11 system (OS) core
|
||||||
|
|
||||||
/// Run the core CPU loop
|
/// Run the core CPU loop
|
||||||
void RunLoop() {
|
void RunLoop() {
|
||||||
// TODO(ShizZy): ImplementMe
|
for (;;){
|
||||||
|
g_app_core->Run(10000);
|
||||||
|
HW::Update();
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/// Step the CPU one instruction
|
/// Step the CPU one instruction
|
||||||
void SingleStep() {
|
void SingleStep() {
|
||||||
g_app_core->Step();
|
g_app_core->Step();
|
||||||
HW::Update();
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/// Halt the core
|
/// Halt the core
|
||||||
|
|
Loading…
Reference in a new issue