stuff/suyu
stuff/suyu
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/suyu.git synced 2024-11-29 14:57:41 -05:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

Merge pull request #3070 from ReinUsesLisp/shader-warnings

Browse source 
shader_ir: Reduce severity of warnings
This commit is contained in:
bunnei 2019-11-07 00:47:24 -05:00 committed by GitHub
commit 344d15f61e
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
7 changed files with 19 additions and 51 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
src/video_core/shader/decode/arithmetic.cpp
View file

@ -43,11 +43,11 @@ u32 ShaderIR::DecodeArithmetic(NodeBlock& bb, u32 pc) {
case OpCode::Id::FMUL_IMM: { case OpCode::Id::FMUL_IMM: {
// FMUL does not have 'abs' bits and only the second operand has a 'neg' bit. // FMUL does not have 'abs' bits and only the second operand has a 'neg' bit.
if (instr.fmul.tab5cb8_2 != 0) { if (instr.fmul.tab5cb8_2 != 0) {
LOG_WARNING(HW_GPU, "FMUL tab5cb8_2({}) is not implemented", LOG_DEBUG(HW_GPU, "FMUL tab5cb8_2({}) is not implemented",
instr.fmul.tab5cb8_2.Value()); instr.fmul.tab5cb8_2.Value());
} }
if (instr.fmul.tab5c68_0 != 1) { if (instr.fmul.tab5c68_0 != 1) {
LOG_WARNING(HW_GPU, "FMUL tab5cb8_0({}) is not implemented", LOG_DEBUG(HW_GPU, "FMUL tab5cb8_0({}) is not implemented",
instr.fmul.tab5c68_0.Value()); instr.fmul.tab5c68_0.Value());
} }
@ -144,10 +144,11 @@ u32 ShaderIR::DecodeArithmetic(NodeBlock& bb, u32 pc) {
case OpCode::Id::RRO_C: case OpCode::Id::RRO_C:
case OpCode::Id::RRO_R: case OpCode::Id::RRO_R:
case OpCode::Id::RRO_IMM: { case OpCode::Id::RRO_IMM: {
LOG_DEBUG(HW_GPU, "(STUBBED) RRO used");
// Currently RRO is only implemented as a register move. // Currently RRO is only implemented as a register move.
op_b = GetOperandAbsNegFloat(op_b, instr.alu.abs_b, instr.alu.negate_b); op_b = GetOperandAbsNegFloat(op_b, instr.alu.abs_b, instr.alu.negate_b);
SetRegister(bb, instr.gpr0, op_b); SetRegister(bb, instr.gpr0, op_b);
LOG_WARNING(HW_GPU, "RRO instruction is incomplete");
break; break;
} }
default: default:

4
src/video_core/shader/decode/arithmetic_half.cpp
View file

@ -21,8 +21,8 @@ u32 ShaderIR::DecodeArithmeticHalf(NodeBlock& bb, u32 pc) {
if (opcode->get().GetId() == OpCode::Id::HADD2_C || if (opcode->get().GetId() == OpCode::Id::HADD2_C ||
opcode->get().GetId() == OpCode::Id::HADD2_R) { opcode->get().GetId() == OpCode::Id::HADD2_R) {
if (instr.alu_half.ftz != 0) { if (instr.alu_half.ftz == 0) {
LOG_WARNING(HW_GPU, "{} FTZ not implemented", opcode->get().GetName()); LOG_DEBUG(HW_GPU, "{} without FTZ is not implemented", opcode->get().GetName());
} }
} }

8
src/video_core/shader/decode/arithmetic_half_immediate.cpp
View file

@ -19,12 +19,12 @@ u32 ShaderIR::DecodeArithmeticHalfImmediate(NodeBlock& bb, u32 pc) {
const auto opcode = OpCode::Decode(instr); const auto opcode = OpCode::Decode(instr);
if (opcode->get().GetId() == OpCode::Id::HADD2_IMM) { if (opcode->get().GetId() == OpCode::Id::HADD2_IMM) {
if (instr.alu_half_imm.ftz != 0) { if (instr.alu_half_imm.ftz == 0) {
LOG_WARNING(HW_GPU, "{} FTZ not implemented", opcode->get().GetName()); LOG_DEBUG(HW_GPU, "{} without FTZ is not implemented", opcode->get().GetName());
} }
} else { } else {
if (instr.alu_half_imm.precision != Tegra::Shader::HalfPrecision::None) { if (instr.alu_half_imm.precision != Tegra::Shader::HalfPrecision::FTZ) {
LOG_WARNING(HW_GPU, "{} FTZ not implemented", opcode->get().GetName()); LOG_DEBUG(HW_GPU, "{} without FTZ is not implemented", opcode->get().GetName());
} }
} }

4
src/video_core/shader/decode/ffma.cpp
View file

@ -19,10 +19,10 @@ u32 ShaderIR::DecodeFfma(NodeBlock& bb, u32 pc) {
UNIMPLEMENTED_IF_MSG(instr.ffma.cc != 0, "FFMA cc not implemented"); UNIMPLEMENTED_IF_MSG(instr.ffma.cc != 0, "FFMA cc not implemented");
if (instr.ffma.tab5980_0 != 1) { if (instr.ffma.tab5980_0 != 1) {
LOG_WARNING(HW_GPU, "FFMA tab5980_0({}) not implemented", instr.ffma.tab5980_0.Value()); LOG_DEBUG(HW_GPU, "FFMA tab5980_0({}) not implemented", instr.ffma.tab5980_0.Value());
} }
if (instr.ffma.tab5980_1 != 0) { if (instr.ffma.tab5980_1 != 0) {
LOG_WARNING(HW_GPU, "FFMA tab5980_1({}) not implemented", instr.ffma.tab5980_1.Value()); LOG_DEBUG(HW_GPU, "FFMA tab5980_1({}) not implemented", instr.ffma.tab5980_1.Value());
} }
const Node op_a = GetRegister(instr.gpr8); const Node op_a = GetRegister(instr.gpr8);

4
src/video_core/shader/decode/half_set.cpp
View file

@ -20,8 +20,8 @@ u32 ShaderIR::DecodeHalfSet(NodeBlock& bb, u32 pc) {
const Instruction instr = {program_code[pc]}; const Instruction instr = {program_code[pc]};
const auto opcode = OpCode::Decode(instr); const auto opcode = OpCode::Decode(instr);
if (instr.hset2.ftz != 0) { if (instr.hset2.ftz == 0) {
LOG_WARNING(HW_GPU, "{} FTZ not implemented", opcode->get().GetName()); LOG_DEBUG(HW_GPU, "{} without FTZ is not implemented", opcode->get().GetName());
} }
Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.hset2.type_a); Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.hset2.type_a);

4
src/video_core/shader/decode/half_set_predicate.cpp
View file

@ -19,7 +19,9 @@ u32 ShaderIR::DecodeHalfSetPredicate(NodeBlock& bb, u32 pc) {
const Instruction instr = {program_code[pc]}; const Instruction instr = {program_code[pc]};
const auto opcode = OpCode::Decode(instr); const auto opcode = OpCode::Decode(instr);
LOG_DEBUG(HW_GPU, "ftz={}", static_cast<u32>(instr.hsetp2.ftz)); if (instr.hsetp2.ftz != 0) {
LOG_DEBUG(HW_GPU, "{} without FTZ is not implemented", opcode->get().GetName());
}
Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.hsetp2.type_a); Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.hsetp2.type_a);
op_a = GetOperandAbsNegHalf(op_a, instr.hsetp2.abs_a, instr.hsetp2.negate_a); op_a = GetOperandAbsNegHalf(op_a, instr.hsetp2.abs_a, instr.hsetp2.negate_a);

35
src/video_core/shader/decode/texture.cpp
View file

@ -44,10 +44,6 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
bool is_bindless = false; bool is_bindless = false;
switch (opcode->get().GetId()) { switch (opcode->get().GetId()) {
case OpCode::Id::TEX: { case OpCode::Id::TEX: {
if (instr.tex.UsesMiscMode(TextureMiscMode::NODEP)) {
LOG_WARNING(HW_GPU, "TEX.NODEP implementation is incomplete");
}
const TextureType texture_type{instr.tex.texture_type}; const TextureType texture_type{instr.tex.texture_type};
const bool is_array = instr.tex.array != 0; const bool is_array = instr.tex.array != 0;
const bool is_aoffi = instr.tex.UsesMiscMode(TextureMiscMode::AOFFI); const bool is_aoffi = instr.tex.UsesMiscMode(TextureMiscMode::AOFFI);
@ -62,10 +58,6 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
UNIMPLEMENTED_IF_MSG(instr.tex.UsesMiscMode(TextureMiscMode::AOFFI), UNIMPLEMENTED_IF_MSG(instr.tex.UsesMiscMode(TextureMiscMode::AOFFI),
"AOFFI is not implemented"); "AOFFI is not implemented");
if (instr.tex.UsesMiscMode(TextureMiscMode::NODEP)) {
LOG_WARNING(HW_GPU, "TEX.NODEP implementation is incomplete");
}
const TextureType texture_type{instr.tex_b.texture_type}; const TextureType texture_type{instr.tex_b.texture_type};
const bool is_array = instr.tex_b.array != 0; const bool is_array = instr.tex_b.array != 0;
const bool is_aoffi = instr.tex.UsesMiscMode(TextureMiscMode::AOFFI); const bool is_aoffi = instr.tex.UsesMiscMode(TextureMiscMode::AOFFI);
@ -82,10 +74,6 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
const bool depth_compare = instr.texs.UsesMiscMode(TextureMiscMode::DC); const bool depth_compare = instr.texs.UsesMiscMode(TextureMiscMode::DC);
const auto process_mode = instr.texs.GetTextureProcessMode(); const auto process_mode = instr.texs.GetTextureProcessMode();
if (instr.texs.UsesMiscMode(TextureMiscMode::NODEP)) {
LOG_WARNING(HW_GPU, "TEXS.NODEP implementation is incomplete");
}
const Node4 components = const Node4 components =
GetTexsCode(instr, texture_type, process_mode, depth_compare, is_array); GetTexsCode(instr, texture_type, process_mode, depth_compare, is_array);
@ -107,10 +95,6 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
UNIMPLEMENTED_IF_MSG(instr.tld4.UsesMiscMode(TextureMiscMode::PTP), UNIMPLEMENTED_IF_MSG(instr.tld4.UsesMiscMode(TextureMiscMode::PTP),
"PTP is not implemented"); "PTP is not implemented");
if (instr.tld4.UsesMiscMode(TextureMiscMode::NODEP)) {
LOG_WARNING(HW_GPU, "TLD4.NODEP implementation is incomplete");
}
const auto texture_type = instr.tld4.texture_type.Value(); const auto texture_type = instr.tld4.texture_type.Value();
const bool depth_compare = is_bindless ? instr.tld4_b.UsesMiscMode(TextureMiscMode::DC) const bool depth_compare = is_bindless ? instr.tld4_b.UsesMiscMode(TextureMiscMode::DC)
: instr.tld4.UsesMiscMode(TextureMiscMode::DC); : instr.tld4.UsesMiscMode(TextureMiscMode::DC);
@ -125,9 +109,6 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
case OpCode::Id::TLD4S: { case OpCode::Id::TLD4S: {
UNIMPLEMENTED_IF_MSG(instr.tld4s.UsesMiscMode(TextureMiscMode::AOFFI), UNIMPLEMENTED_IF_MSG(instr.tld4s.UsesMiscMode(TextureMiscMode::AOFFI),
"AOFFI is not implemented"); "AOFFI is not implemented");
if (instr.tld4s.UsesMiscMode(TextureMiscMode::NODEP)) {
LOG_WARNING(HW_GPU, "TLD4S.NODEP implementation is incomplete");
}
const bool depth_compare = instr.tld4s.UsesMiscMode(TextureMiscMode::DC); const bool depth_compare = instr.tld4s.UsesMiscMode(TextureMiscMode::DC);
const Node op_a = GetRegister(instr.gpr8); const Node op_a = GetRegister(instr.gpr8);
@ -164,10 +145,6 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
is_bindless = true; is_bindless = true;
[[fallthrough]]; [[fallthrough]];
case OpCode::Id::TXQ: { case OpCode::Id::TXQ: {
if (instr.txq.UsesMiscMode(TextureMiscMode::NODEP)) {
LOG_WARNING(HW_GPU, "TXQ.NODEP implementation is incomplete");
}
// TODO: The new commits on the texture refactor, change the way samplers work. // TODO: The new commits on the texture refactor, change the way samplers work.
// Sadly, not all texture instructions specify the type of texture their sampler // Sadly, not all texture instructions specify the type of texture their sampler
// uses. This must be fixed at a later instance. // uses. This must be fixed at a later instance.
@ -205,10 +182,6 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
UNIMPLEMENTED_IF_MSG(instr.tmml.UsesMiscMode(Tegra::Shader::TextureMiscMode::NDV), UNIMPLEMENTED_IF_MSG(instr.tmml.UsesMiscMode(Tegra::Shader::TextureMiscMode::NDV),
"NDV is not implemented"); "NDV is not implemented");
if (instr.tmml.UsesMiscMode(TextureMiscMode::NODEP)) {
LOG_WARNING(HW_GPU, "TMML.NODEP implementation is incomplete");
}
auto texture_type = instr.tmml.texture_type.Value(); auto texture_type = instr.tmml.texture_type.Value();
const bool is_array = instr.tmml.array != 0; const bool is_array = instr.tmml.array != 0;
const auto& sampler = const auto& sampler =
@ -254,10 +227,6 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
UNIMPLEMENTED_IF_MSG(instr.tld.ms, "MS is not implemented"); UNIMPLEMENTED_IF_MSG(instr.tld.ms, "MS is not implemented");
UNIMPLEMENTED_IF_MSG(instr.tld.cl, "CL is not implemented"); UNIMPLEMENTED_IF_MSG(instr.tld.cl, "CL is not implemented");
if (instr.tld.nodep_flag) {
LOG_WARNING(HW_GPU, "TLD.NODEP implementation is incomplete");
}
WriteTexInstructionFloat(bb, instr, GetTldCode(instr)); WriteTexInstructionFloat(bb, instr, GetTldCode(instr));
break; break;
} }
@ -269,10 +238,6 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
"AOFFI is not implemented"); "AOFFI is not implemented");
UNIMPLEMENTED_IF_MSG(instr.tlds.UsesMiscMode(TextureMiscMode::MZ), "MZ is not implemented"); UNIMPLEMENTED_IF_MSG(instr.tlds.UsesMiscMode(TextureMiscMode::MZ), "MZ is not implemented");
if (instr.tlds.UsesMiscMode(TextureMiscMode::NODEP)) {
LOG_WARNING(HW_GPU, "TLDS.NODEP implementation is incomplete");
}
const Node4 components = GetTldsCode(instr, texture_type, is_array); const Node4 components = GetTldsCode(instr, texture_type, is_array);
if (instr.tlds.fp32_flag) { if (instr.tlds.fp32_flag) {