stuff/suyu
stuff/suyu
1
0
Fork 0
mirror of https://git.suyu.dev/suyu/suyu.git synced 2024-11-25 04:46:27 -05:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

shader: Implement IADD3.CC/.X

Browse source
This commit is contained in:
FernandoS27 2021-04-14 03:41:37 +02:00 committed by ameerj
parent f69d0b91ff
commit 21a878237b
1 changed files with 22 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

29
src/shader_recompiler/frontend/maxwell/translate/impl/integer_add_three_input.cpp
View file

@ -58,13 +58,6 @@ void IADD3(TranslatorVisitor& v, u64 insn, IR::U32 op_b, IR::U32 op_c) {
BitField<51, 1, u64> neg_a; BitField<51, 1, u64> neg_a;
} iadd3{insn}; } iadd3{insn};
if (iadd3.x != 0) {
throw NotImplementedException("IADD3 X");
}
if (iadd3.cc != 0) {
throw NotImplementedException("IADD3 CC");
}
IR::U32 op_a{v.X(iadd3.src_a)}; IR::U32 op_a{v.X(iadd3.src_a)};
op_a = IntegerHalf(v.ir, op_a, iadd3.half_a); op_a = IntegerHalf(v.ir, op_a, iadd3.half_a);
op_b = IntegerHalf(v.ir, op_b, iadd3.half_b); op_b = IntegerHalf(v.ir, op_b, iadd3.half_b);
@ -81,10 +74,32 @@ void IADD3(TranslatorVisitor& v, u64 insn, IR::U32 op_b, IR::U32 op_c) {
} }
IR::U32 lhs{v.ir.IAdd(op_a, op_b)}; IR::U32 lhs{v.ir.IAdd(op_a, op_b)};
IR::U1 of_1;
if (iadd3.cc != 0) {
of_1 = v.ir.GetOverflowFromOp(lhs);
}
if (iadd3.x != 0) {
const IR::U32 carry{v.ir.Select(v.ir.GetCFlag(), v.ir.Imm32(1), v.ir.Imm32(0))};
lhs = v.ir.IAdd(lhs, carry);
}
if (iadd3.cc != 0 && iadd3.shift == Shift::Left) {
IR::U32 high_bits{v.ir.ShiftRightLogical(lhs, v.ir.Imm32(16))};
of_1 = v.ir.LogicalOr(of_1, v.ir.INotEqual(v.ir.Imm32(0), high_bits));
}
lhs = IntegerShift(v.ir, lhs, iadd3.shift); lhs = IntegerShift(v.ir, lhs, iadd3.shift);
const IR::U32 result{v.ir.IAdd(lhs, op_c)}; const IR::U32 result{v.ir.IAdd(lhs, op_c)};
v.X(iadd3.dest_reg, result); v.X(iadd3.dest_reg, result);
if (iadd3.cc != 0) {
// TODO: How does CC behave when X is set?
if (iadd3.x != 0) {
throw NotImplementedException("IADD3 X+CC");
}
v.SetZFlag(v.ir.GetZeroFromOp(result));
v.SetSFlag(v.ir.GetSignFromOp(result));
v.SetCFlag(v.ir.GetCarryFromOp(result));
v.SetOFlag(v.ir.LogicalOr(v.ir.GetOverflowFromOp(result), of_1));
}
} }
} // Anonymous namespace } // Anonymous namespace