mirror of
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Common: Cleanup CPU capability detection code.
This commit is contained in:
bunnei
parent
a1942238f5
commit
0ee00861f6
5 changed files with 144 additions and 201 deletions
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@ -1,23 +1,25 @@
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// Copyright 2008 Dolphin Emulator Project
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// Licensed under GPLv2+
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// Copyright 2013 Dolphin Emulator Project / 2015 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <cstring>
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#include <string>
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#include <thread>
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#include "common/common_types.h"
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#include "cpu_detect.h"
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#ifndef _WIN32
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namespace Common {
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#ifndef _MSC_VER
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#ifdef __FreeBSD__
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#include <sys/types.h>
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#include <machine/cpufunc.h>
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#endif
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static inline void __cpuidex(int info[4], int function_id, int subfunction_id)
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{
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static inline void __cpuidex(int info[4], int function_id, int subfunction_id) {
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#ifdef __FreeBSD__
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// Despite the name, this is just do_cpuid() with ECX as second input.
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cpuid_count((u_int)function_id, (u_int)subfunction_id, (u_int*)info);
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@ -36,96 +38,67 @@ static inline void __cpuidex(int info[4], int function_id, int subfunction_id)
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#endif
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}
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static inline void __cpuid(int info[4], int function_id)
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{
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static inline void __cpuid(int info[4], int function_id) {
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return __cpuidex(info, function_id, 0);
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}
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#define _XCR_XFEATURE_ENABLED_MASK 0
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static u64 _xgetbv(u32 index)
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{
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static u64 _xgetbv(u32 index) {
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u32 eax, edx;
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__asm__ __volatile__("xgetbv" : "=a"(eax), "=d"(edx) : "c"(index));
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return ((u64)edx << 32) | eax;
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}
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#endif // ifndef _WIN32
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namespace Common {
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CPUInfo cpu_info;
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CPUInfo::CPUInfo() {
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Detect();
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}
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#endif // ifndef _MSC_VER
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// Detects the various CPU features
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void CPUInfo::Detect() {
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memset(this, 0, sizeof(*this));
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#ifdef ARCHITECTURE_X64
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Mode64bit = true;
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OS64bit = true;
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#endif
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num_cores = 1;
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static CPUCaps Detect() {
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CPUCaps caps = {};
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// Set obvious defaults, for extra safety
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if (Mode64bit) {
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bSSE = true;
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bSSE2 = true;
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bLongMode = true;
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}
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caps.num_cores = std::thread::hardware_concurrency();
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// Assumes the CPU supports the CPUID instruction. Those that don't would likely not support
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// Citra at all anyway
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// Assume CPU supports the CPUID instruction. Those that don't can barely
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// boot modern OS:es anyway.
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int cpu_id[4];
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memset(brand_string, 0, sizeof(brand_string));
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memset(caps.brand_string, 0, sizeof(caps.brand_string));
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// Detect CPU's CPUID capabilities, and grab CPU string
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// Detect CPU's CPUID capabilities and grab CPU string
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__cpuid(cpu_id, 0x00000000);
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u32 max_std_fn = cpu_id[0]; // EAX
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*((int *)brand_string) = cpu_id[1];
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*((int *)(brand_string + 4)) = cpu_id[3];
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*((int *)(brand_string + 8)) = cpu_id[2];
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u32 max_std_fn = cpu_id[0]; // EAX
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std::memcpy(&caps.brand_string[0], &cpu_id[1], sizeof(int));
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std::memcpy(&caps.brand_string[4], &cpu_id[3], sizeof(int));
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std::memcpy(&caps.brand_string[8], &cpu_id[2], sizeof(int));
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__cpuid(cpu_id, 0x80000000);
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u32 max_ex_fn = cpu_id[0];
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if (!strcmp(brand_string, "GenuineIntel"))
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vendor = VENDOR_INTEL;
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else if (!strcmp(brand_string, "AuthenticAMD"))
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vendor = VENDOR_AMD;
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if (!strcmp(caps.brand_string, "GenuineIntel"))
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caps.vendor = CPUVendor::INTEL;
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else if (!strcmp(caps.brand_string, "AuthenticAMD"))
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caps.vendor = CPUVendor::AMD;
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else
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vendor = VENDOR_OTHER;
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caps.vendor = CPUVendor::OTHER;
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// Set reasonable default brand string even if brand string not available.
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strcpy(cpu_string, brand_string);
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// Set reasonable default brand string even if brand string not available
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strcpy(caps.cpu_string, caps.brand_string);
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// Detect family and other misc stuff.
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bool ht = false;
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HTT = ht;
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logical_cpu_count = 1;
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// Detect family and other miscellaneous features
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if (max_std_fn >= 1) {
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__cpuid(cpu_id, 0x00000001);
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int family = ((cpu_id[0] >> 8) & 0xf) + ((cpu_id[0] >> 20) & 0xff);
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int model = ((cpu_id[0] >> 4) & 0xf) + ((cpu_id[0] >> 12) & 0xf0);
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// Detect people unfortunate enough to be running Dolphin on an Atom
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if (family == 6 && (model == 0x1C || model == 0x26 || model == 0x27 || model == 0x35 || model == 0x36 ||
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model == 0x37 || model == 0x4A || model == 0x4D || model == 0x5A || model == 0x5D))
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bAtom = true;
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logical_cpu_count = (cpu_id[1] >> 16) & 0xFF;
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ht = (cpu_id[3] >> 28) & 1;
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if ((cpu_id[3] >> 25) & 1) bSSE = true;
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if ((cpu_id[3] >> 26) & 1) bSSE2 = true;
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if ((cpu_id[2]) & 1) bSSE3 = true;
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if ((cpu_id[2] >> 9) & 1) bSSSE3 = true;
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if ((cpu_id[2] >> 19) & 1) bSSE4_1 = true;
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if ((cpu_id[2] >> 20) & 1) bSSE4_2 = true;
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if ((cpu_id[2] >> 22) & 1) bMOVBE = true;
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if ((cpu_id[2] >> 25) & 1) bAES = true;
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if ((cpu_id[3] >> 25) & 1) caps.sse = true;
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if ((cpu_id[3] >> 26) & 1) caps.sse2 = true;
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if ((cpu_id[2]) & 1) caps.sse3 = true;
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if ((cpu_id[2] >> 9) & 1) caps.ssse3 = true;
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if ((cpu_id[2] >> 19) & 1) caps.sse4_1 = true;
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if ((cpu_id[2] >> 20) & 1) caps.sse4_2 = true;
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if ((cpu_id[2] >> 22) & 1) caps.movbe = true;
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if ((cpu_id[2] >> 25) & 1) caps.aes = true;
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if ((cpu_id[3] >> 24) & 1)
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{
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// We can use FXSAVE.
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bFXSR = true;
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if ((cpu_id[3] >> 24) & 1) {
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caps.fxsave_fxrstor = true;
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}
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// AVX support requires 3 separate checks:
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@ -134,95 +107,80 @@ void CPUInfo::Detect() {
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// - XGETBV result has the XCR bit set.
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if (((cpu_id[2] >> 28) & 1) && ((cpu_id[2] >> 27) & 1)) {
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if ((_xgetbv(_XCR_XFEATURE_ENABLED_MASK) & 0x6) == 0x6) {
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bAVX = true;
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caps.avx = true;
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if ((cpu_id[2] >> 12) & 1)
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bFMA = true;
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caps.fma = true;
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}
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}
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if (max_std_fn >= 7) {
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__cpuidex(cpu_id, 0x00000007, 0x00000000);
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// careful; we can't enable AVX2 unless the XSAVE/XGETBV checks above passed
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// Can't enable AVX2 unless the XSAVE/XGETBV checks above passed
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if ((cpu_id[1] >> 5) & 1)
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bAVX2 = bAVX;
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caps.avx2 = caps.avx;
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if ((cpu_id[1] >> 3) & 1)
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bBMI1 = true;
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caps.bmi1 = true;
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if ((cpu_id[1] >> 8) & 1)
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bBMI2 = true;
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caps.bmi2 = true;
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}
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}
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bFlushToZero = bSSE;
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caps.flush_to_zero = caps.sse;
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if (max_ex_fn >= 0x80000004) {
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// Extract CPU model string
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__cpuid(cpu_id, 0x80000002);
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memcpy(cpu_string, cpu_id, sizeof(cpu_id));
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std::memcpy(caps.cpu_string, cpu_id, sizeof(cpu_id));
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__cpuid(cpu_id, 0x80000003);
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memcpy(cpu_string + 16, cpu_id, sizeof(cpu_id));
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std::memcpy(caps.cpu_string + 16, cpu_id, sizeof(cpu_id));
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__cpuid(cpu_id, 0x80000004);
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memcpy(cpu_string + 32, cpu_id, sizeof(cpu_id));
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std::memcpy(caps.cpu_string + 32, cpu_id, sizeof(cpu_id));
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}
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if (max_ex_fn >= 0x80000001) {
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// Check for more features.
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// Check for more features
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__cpuid(cpu_id, 0x80000001);
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if (cpu_id[2] & 1) bLAHFSAHF64 = true;
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if ((cpu_id[2] >> 5) & 1) bLZCNT = true;
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if ((cpu_id[2] >> 16) & 1) bFMA4 = true;
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if ((cpu_id[3] >> 29) & 1) bLongMode = true;
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if (cpu_id[2] & 1) caps.lahf_sahf_64 = true;
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if ((cpu_id[2] >> 5) & 1) caps.lzcnt = true;
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if ((cpu_id[2] >> 16) & 1) caps.fma4 = true;
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if ((cpu_id[3] >> 29) & 1) caps.long_mode = true;
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}
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num_cores = (logical_cpu_count == 0) ? 1 : logical_cpu_count;
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if (max_ex_fn >= 0x80000008) {
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// Get number of cores. This is a bit complicated. Following AMD manual here.
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__cpuid(cpu_id, 0x80000008);
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int apic_id_core_id_size = (cpu_id[2] >> 12) & 0xF;
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if (apic_id_core_id_size == 0) {
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if (ht) {
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// New mechanism for modern Intel CPUs.
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if (vendor == VENDOR_INTEL) {
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__cpuidex(cpu_id, 0x00000004, 0x00000000);
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int cores_x_package = ((cpu_id[0] >> 26) & 0x3F) + 1;
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HTT = (cores_x_package < logical_cpu_count);
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cores_x_package = ((logical_cpu_count % cores_x_package) == 0) ? cores_x_package : 1;
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num_cores = (cores_x_package > 1) ? cores_x_package : num_cores;
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logical_cpu_count /= cores_x_package;
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}
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}
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} else {
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// Use AMD's new method.
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num_cores = (cpu_id[2] & 0xFF) + 1;
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}
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}
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return caps;
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}
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// Turn the CPU info into a string we can show
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std::string CPUInfo::Summarize() {
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std::string sum(cpu_string);
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const CPUCaps& GetCPUCaps() {
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static CPUCaps caps = Detect();
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return caps;
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}
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std::string GetCPUCapsString() {
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auto caps = GetCPUCaps();
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std::string sum(caps.cpu_string);
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sum += " (";
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sum += brand_string;
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sum += caps.brand_string;
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sum += ")";
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if (bSSE) sum += ", SSE";
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if (bSSE2) {
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if (caps.sse) sum += ", SSE";
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if (caps.sse2) {
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sum += ", SSE2";
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if (!bFlushToZero)
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sum += " (but not DAZ!)";
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if (!caps.flush_to_zero) sum += " (without DAZ)";
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}
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if (bSSE3) sum += ", SSE3";
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if (bSSSE3) sum += ", SSSE3";
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if (bSSE4_1) sum += ", SSE4.1";
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if (bSSE4_2) sum += ", SSE4.2";
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if (HTT) sum += ", HTT";
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if (bAVX) sum += ", AVX";
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if (bAVX2) sum += ", AVX2";
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if (bBMI1) sum += ", BMI1";
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if (bBMI2) sum += ", BMI2";
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if (bFMA) sum += ", FMA";
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if (bAES) sum += ", AES";
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if (bMOVBE) sum += ", MOVBE";
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if (bLongMode) sum += ", 64-bit support";
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if (caps.sse3) sum += ", SSE3";
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if (caps.ssse3) sum += ", SSSE3";
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if (caps.sse4_1) sum += ", SSE4.1";
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if (caps.sse4_2) sum += ", SSE4.2";
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if (caps.avx) sum += ", AVX";
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if (caps.avx2) sum += ", AVX2";
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if (caps.bmi1) sum += ", BMI1";
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if (caps.bmi2) sum += ", BMI2";
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if (caps.fma) sum += ", FMA";
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if (caps.aes) sum += ", AES";
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if (caps.movbe) sum += ", MOVBE";
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if (caps.long_mode) sum += ", 64-bit support";
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return sum;
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}
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@ -1,81 +1,66 @@
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// Copyright 2013 Dolphin Emulator Project / 2014 Citra Emulator Project
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// Copyright 2013 Dolphin Emulator Project / 2015 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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// Detect the CPU, so we'll know which optimizations to use
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#pragma once
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#include <string>
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namespace Common {
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enum CPUVendor
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{
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VENDOR_INTEL = 0,
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VENDOR_AMD = 1,
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VENDOR_ARM = 2,
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VENDOR_OTHER = 3,
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/// x86/x64 CPU vendors that may be detected by this module
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enum class CPUVendor {
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INTEL,
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AMD,
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OTHER,
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};
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struct CPUInfo
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{
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/// x86/x64 CPU capabilities that may be detected by this module
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struct CPUCaps {
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CPUVendor vendor;
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char cpu_string[0x21];
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char brand_string[0x41];
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bool OS64bit;
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bool CPU64bit;
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bool Mode64bit;
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bool HTT;
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int num_cores;
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int logical_cpu_count;
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bool sse;
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bool sse2;
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bool sse3;
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bool ssse3;
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bool sse4_1;
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bool sse4_2;
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bool lzcnt;
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bool avx;
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bool avx2;
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bool bmi1;
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bool bmi2;
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bool fma;
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bool fma4;
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bool aes;
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bool bSSE;
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bool bSSE2;
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bool bSSE3;
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bool bSSSE3;
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bool bPOPCNT;
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bool bSSE4_1;
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bool bSSE4_2;
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bool bLZCNT;
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bool bSSE4A;
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bool bAVX;
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bool bAVX2;
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bool bBMI1;
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bool bBMI2;
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bool bFMA;
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bool bFMA4;
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bool bAES;
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// FXSAVE/FXRSTOR
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bool bFXSR;
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bool bMOVBE;
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// This flag indicates that the hardware supports some mode
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// in which denormal inputs _and_ outputs are automatically set to (signed) zero.
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bool bFlushToZero;
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bool bLAHFSAHF64;
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bool bLongMode;
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bool bAtom;
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// Support for the FXSAVE and FXRSTOR instructions
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bool fxsave_fxrstor;
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// ARMv8 specific
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bool bFP;
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bool bASIMD;
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bool bCRC32;
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bool bSHA1;
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bool bSHA2;
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bool movbe;
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// Call Detect()
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explicit CPUInfo();
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// This flag indicates that the hardware supports some mode in which denormal inputs and outputs
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// are automatically set to (signed) zero.
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bool flush_to_zero;
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// Turn the cpu info into a string we can show
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std::string Summarize();
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// Support for LAHF and SAHF instructions in 64-bit mode
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bool lahf_sahf_64;
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private:
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// Detects the various cpu features
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void Detect();
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bool long_mode;
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};
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extern CPUInfo cpu_info;
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/**
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* Gets the supported capabilities of the host CPU
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* @return Reference to a CPUCaps struct with the detected host CPU capabilities
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*/
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const CPUCaps& GetCPUCaps();
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/**
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* Gets a string summary of the name and supported capabilities of the host CPU
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* @return String summary
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*/
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std::string GetCPUCapsString();
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} // namespace Common
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@ -826,14 +826,14 @@ void XEmitter::BSR(int bits, X64Reg dest, OpArg src) {WriteBitSearchType(bits,de
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void XEmitter::TZCNT(int bits, X64Reg dest, OpArg src)
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{
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CheckFlags();
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if (!Common::cpu_info.bBMI1)
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if (!Common::GetCPUCaps().bmi1)
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ASSERT_MSG(0, "Trying to use BMI1 on a system that doesn't support it. Bad programmer.");
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WriteBitSearchType(bits, dest, src, 0xBC, true);
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}
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void XEmitter::LZCNT(int bits, X64Reg dest, OpArg src)
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{
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CheckFlags();
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if (!Common::cpu_info.bLZCNT)
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if (!Common::GetCPUCaps().lzcnt)
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ASSERT_MSG(0, "Trying to use LZCNT on a system that doesn't support it. Bad programmer.");
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WriteBitSearchType(bits, dest, src, 0xBD, true);
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}
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||||
|
|
@ -907,7 +907,7 @@ void XEmitter::MOVZX(int dbits, int sbits, X64Reg dest, OpArg src)
|
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|
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void XEmitter::MOVBE(int bits, const OpArg& dest, const OpArg& src)
|
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{
|
||||
ASSERT_MSG(Common::cpu_info.bMOVBE, "Generating MOVBE on a system that does not support it.");
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ASSERT_MSG(Common::GetCPUCaps().movbe, "Generating MOVBE on a system that does not support it.");
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if (bits == 8)
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{
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MOV(bits, dest, src);
|
||||
|
|
@ -1420,7 +1420,7 @@ static int GetVEXpp(u8 opPrefix)
|
|||
|
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void XEmitter::WriteAVXOp(u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes)
|
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{
|
||||
if (!Common::cpu_info.bAVX)
|
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if (!Common::GetCPUCaps().avx)
|
||||
ASSERT_MSG(0, "Trying to use AVX on a system that doesn't support it. Bad programmer.");
|
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int mmmmm = GetVEXmmmmm(op);
|
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int pp = GetVEXpp(opPrefix);
|
||||
|
|
@ -1445,7 +1445,7 @@ void XEmitter::WriteVEXOp(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg r
|
|||
void XEmitter::WriteBMI1Op(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes)
|
||||
{
|
||||
CheckFlags();
|
||||
if (!Common::cpu_info.bBMI1)
|
||||
if (!Common::GetCPUCaps().bmi1)
|
||||
ASSERT_MSG(0, "Trying to use BMI1 on a system that doesn't support it. Bad programmer.");
|
||||
WriteVEXOp(size, opPrefix, op, regOp1, regOp2, arg, extrabytes);
|
||||
}
|
||||
|
|
@ -1453,7 +1453,7 @@ void XEmitter::WriteBMI1Op(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg
|
|||
void XEmitter::WriteBMI2Op(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes)
|
||||
{
|
||||
CheckFlags();
|
||||
if (!Common::cpu_info.bBMI2)
|
||||
if (!Common::GetCPUCaps().bmi2)
|
||||
ASSERT_MSG(0, "Trying to use BMI2 on a system that doesn't support it. Bad programmer.");
|
||||
WriteVEXOp(size, opPrefix, op, regOp1, regOp2, arg, extrabytes);
|
||||
}
|
||||
|
|
@ -1647,7 +1647,7 @@ void XEmitter::UNPCKHPD(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0x15, dest, ar
|
|||
|
||||
void XEmitter::MOVDDUP(X64Reg regOp, OpArg arg)
|
||||
{
|
||||
if (Common::cpu_info.bSSE3)
|
||||
if (Common::GetCPUCaps().sse3)
|
||||
{
|
||||
WriteSSEOp(0xF2, 0x12, regOp, arg); //SSE3 movddup
|
||||
}
|
||||
|
|
@ -1737,14 +1737,14 @@ void XEmitter::PSRAD(X64Reg reg, int shift)
|
|||
|
||||
void XEmitter::WriteSSSE3Op(u8 opPrefix, u16 op, X64Reg regOp, OpArg arg, int extrabytes)
|
||||
{
|
||||
if (!Common::cpu_info.bSSSE3)
|
||||
if (!Common::GetCPUCaps().ssse3)
|
||||
ASSERT_MSG(0, "Trying to use SSSE3 on a system that doesn't support it. Bad programmer.");
|
||||
WriteSSEOp(opPrefix, op, regOp, arg, extrabytes);
|
||||
}
|
||||
|
||||
void XEmitter::WriteSSE41Op(u8 opPrefix, u16 op, X64Reg regOp, OpArg arg, int extrabytes)
|
||||
{
|
||||
if (!Common::cpu_info.bSSE4_1)
|
||||
if (!Common::GetCPUCaps().sse4_1)
|
||||
ASSERT_MSG(0, "Trying to use SSE4.1 on a system that doesn't support it. Bad programmer.");
|
||||
WriteSSEOp(opPrefix, op, regOp, arg, extrabytes);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -532,7 +532,7 @@ public:
|
|||
void MOVSX(int dbits, int sbits, X64Reg dest, OpArg src); //automatically uses MOVSXD if necessary
|
||||
void MOVZX(int dbits, int sbits, X64Reg dest, OpArg src);
|
||||
|
||||
// Available only on Atom or >= Haswell so far. Test with cpu_info.bMOVBE.
|
||||
// Available only on Atom or >= Haswell so far. Test with GetCPUCaps().movbe.
|
||||
void MOVBE(int dbits, const OpArg& dest, const OpArg& src);
|
||||
|
||||
// Available only on AMD >= Phenom or Intel >= Haswell
|
||||
|
|
|
|||
|
|
@ -223,7 +223,7 @@ void JitCompiler::Compile_DestEnable(Instruction instr,X64Reg src) {
|
|||
// Not all components are enabled, so mask the result when storing to the destination register...
|
||||
MOVAPS(SCRATCH, MDisp(STATE, UnitState::OutputOffset(dest)));
|
||||
|
||||
if (Common::cpu_info.bSSE4_1) {
|
||||
if (Common::GetCPUCaps().sse4_1) {
|
||||
u8 mask = ((swiz.dest_mask & 1) << 3) | ((swiz.dest_mask & 8) >> 3) | ((swiz.dest_mask & 2) << 1) | ((swiz.dest_mask & 4) >> 1);
|
||||
BLENDPS(SCRATCH, R(src), mask);
|
||||
} else {
|
||||
|
|
@ -291,7 +291,7 @@ void JitCompiler::Compile_DP3(Instruction instr) {
|
|||
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
|
||||
Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2);
|
||||
|
||||
if (Common::cpu_info.bSSE4_1) {
|
||||
if (Common::GetCPUCaps().sse4_1) {
|
||||
DPPS(SRC1, R(SRC2), 0x7f);
|
||||
} else {
|
||||
MULPS(SRC1, R(SRC2));
|
||||
|
|
@ -314,7 +314,7 @@ void JitCompiler::Compile_DP4(Instruction instr) {
|
|||
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
|
||||
Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2);
|
||||
|
||||
if (Common::cpu_info.bSSE4_1) {
|
||||
if (Common::GetCPUCaps().sse4_1) {
|
||||
DPPS(SRC1, R(SRC2), 0xff);
|
||||
} else {
|
||||
MULPS(SRC1, R(SRC2));
|
||||
|
|
@ -341,7 +341,7 @@ void JitCompiler::Compile_MUL(Instruction instr) {
|
|||
void JitCompiler::Compile_FLR(Instruction instr) {
|
||||
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1);
|
||||
|
||||
if (Common::cpu_info.bSSE4_1) {
|
||||
if (Common::GetCPUCaps().sse4_1) {
|
||||
ROUNDFLOORPS(SRC1, R(SRC1));
|
||||
} else {
|
||||
CVTPS2DQ(SRC1, R(SRC1));
|
||||
|
|
@ -513,7 +513,7 @@ void JitCompiler::Compile_MAD(Instruction instr) {
|
|||
Compile_SwizzleSrc(instr, 3, instr.mad.src3, SRC3);
|
||||
}
|
||||
|
||||
if (Common::cpu_info.bFMA) {
|
||||
if (Common::GetCPUCaps().fma) {
|
||||
VFMADD213PS(SRC1, SRC2, R(SRC3));
|
||||
} else {
|
||||
MULPS(SRC1, R(SRC2));
|
||||
|
|
|
|||
Loading…
Reference in a new issue