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shader_decode: Implement POPC
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parent
55e6786254
commit
027f443e69
4 changed files with 22 additions and 1 deletions
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@ -119,6 +119,16 @@ u32 ShaderIR::DecodeArithmeticInteger(BasicBlock& bb, u32 pc) {
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SetRegister(bb, instr.gpr0, value);
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SetRegister(bb, instr.gpr0, value);
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break;
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break;
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}
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}
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case OpCode::Id::POPC_C:
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case OpCode::Id::POPC_R:
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case OpCode::Id::POPC_IMM: {
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if (instr.popc.invert) {
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op_b = Operation(OperationCode::IBitwiseNot, NO_PRECISE, op_b);
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}
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const Node value = Operation(OperationCode::IBitCount, PRECISE, op_b);
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::SEL_C:
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case OpCode::Id::SEL_C:
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case OpCode::Id::SEL_R:
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case OpCode::Id::SEL_R:
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case OpCode::Id::SEL_IMM: {
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case OpCode::Id::SEL_IMM: {
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@ -908,6 +908,11 @@ private:
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Type::Int);
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Type::Int);
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}
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}
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template <Type type>
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std::string BitCount(Operation operation) {
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return GenerateUnary(operation, "bitCount", type, type, false);
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}
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std::string HNegate(Operation operation) {
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std::string HNegate(Operation operation) {
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const auto GetNegate = [&](std::size_t index) -> std::string {
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const auto GetNegate = [&](std::size_t index) -> std::string {
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if (const auto pred = std::get_if<PredicateNode>(operation[index])) {
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if (const auto pred = std::get_if<PredicateNode>(operation[index])) {
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@ -1273,6 +1278,7 @@ private:
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&BitwiseXor<Type::Int>,
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&BitwiseXor<Type::Int>,
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&BitwiseNot<Type::Int>,
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&BitwiseNot<Type::Int>,
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&BitfieldInsert<Type::Int>,
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&BitfieldInsert<Type::Int>,
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&BitCount<Type::Int>,
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&Add<Type::Uint>,
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&Add<Type::Uint>,
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&Mul<Type::Uint>,
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&Mul<Type::Uint>,
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@ -1289,6 +1295,7 @@ private:
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&BitwiseXor<Type::Uint>,
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&BitwiseXor<Type::Uint>,
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&BitwiseNot<Type::Uint>,
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&BitwiseNot<Type::Uint>,
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&BitfieldInsert<Type::Uint>,
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&BitfieldInsert<Type::Uint>,
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&BitCount<Type::Uint>,
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&Add<Type::HalfFloat>,
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&Add<Type::HalfFloat>,
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&Mul<Type::HalfFloat>,
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&Mul<Type::HalfFloat>,
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@ -386,6 +386,8 @@ void ShaderIR::SetLocalMemory(BasicBlock& bb, Node address, Node value) {
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return OperationCode::UBitwiseNot;
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return OperationCode::UBitwiseNot;
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case OperationCode::IBitfieldInsert:
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case OperationCode::IBitfieldInsert:
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return OperationCode::UBitfieldInsert;
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return OperationCode::UBitfieldInsert;
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case OperationCode::IBitCount:
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return OperationCode::UBitCount;
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case OperationCode::LogicalILessThan:
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case OperationCode::LogicalILessThan:
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return OperationCode::LogicalULessThan;
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return OperationCode::LogicalULessThan;
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case OperationCode::LogicalIEqual:
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case OperationCode::LogicalIEqual:
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@ -89,6 +89,7 @@ enum class OperationCode {
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IBitwiseXor, /// (MetaArithmetic, int a, int b) -> int
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IBitwiseXor, /// (MetaArithmetic, int a, int b) -> int
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IBitwiseNot, /// (MetaArithmetic, int a) -> int
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IBitwiseNot, /// (MetaArithmetic, int a) -> int
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IBitfieldInsert, /// (MetaArithmetic, int base, int insert, int offset, int bits) -> int
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IBitfieldInsert, /// (MetaArithmetic, int base, int insert, int offset, int bits) -> int
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IBitCount, /// (MetaArithmetic, int) -> int
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UAdd, /// (MetaArithmetic, uint a, uint b) -> uint
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UAdd, /// (MetaArithmetic, uint a, uint b) -> uint
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UMul, /// (MetaArithmetic, uint a, uint b) -> uint
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UMul, /// (MetaArithmetic, uint a, uint b) -> uint
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@ -103,8 +104,9 @@ enum class OperationCode {
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UBitwiseAnd, /// (MetaArithmetic, uint a, uint b) -> uint
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UBitwiseAnd, /// (MetaArithmetic, uint a, uint b) -> uint
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UBitwiseOr, /// (MetaArithmetic, uint a, uint b) -> uint
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UBitwiseOr, /// (MetaArithmetic, uint a, uint b) -> uint
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UBitwiseXor, /// (MetaArithmetic, uint a, uint b) -> uint
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UBitwiseXor, /// (MetaArithmetic, uint a, uint b) -> uint
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UBitwiseNot, /// (MetaArithmetic, uint a) -> int
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UBitwiseNot, /// (MetaArithmetic, uint a) -> uint
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UBitfieldInsert, /// (MetaArithmetic, uint base, uint insert, int offset, int bits) -> uint
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UBitfieldInsert, /// (MetaArithmetic, uint base, uint insert, int offset, int bits) -> uint
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UBitCount, /// (MetaArithmetic, uint) -> uint
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HAdd, /// (MetaHalfArithmetic, f16vec2 a, f16vec2 b) -> f16vec2
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HAdd, /// (MetaHalfArithmetic, f16vec2 a, f16vec2 b) -> f16vec2
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HMul, /// (MetaHalfArithmetic, f16vec2 a, f16vec2 b) -> f16vec2
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HMul, /// (MetaHalfArithmetic, f16vec2 a, f16vec2 b) -> f16vec2
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