2018-12-20 17:09:21 -05:00
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// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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2020-04-07 01:16:51 -04:00
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#include <limits>
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#include <optional>
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#include <utility>
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2018-12-20 17:09:21 -05:00
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "video_core/engines/shader_bytecode.h"
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2019-06-04 21:44:06 -04:00
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#include "video_core/shader/node_helper.h"
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2018-12-20 17:09:21 -05:00
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#include "video_core/shader/shader_ir.h"
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namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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2018-12-15 15:32:51 -05:00
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using Tegra::Shader::Register;
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2018-12-20 17:09:21 -05:00
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2019-08-28 15:09:33 -04:00
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namespace {
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2020-04-07 01:16:51 -04:00
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2019-08-28 15:09:33 -04:00
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constexpr OperationCode GetFloatSelector(u64 selector) {
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return selector == 0 ? OperationCode::FCastHalf0 : OperationCode::FCastHalf1;
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}
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2020-04-07 01:16:51 -04:00
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constexpr u32 SizeInBits(Register::Size size) {
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switch (size) {
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case Register::Size::Byte:
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return 8;
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case Register::Size::Short:
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return 16;
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case Register::Size::Word:
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return 32;
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case Register::Size::Long:
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return 64;
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}
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return 0;
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}
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constexpr std::optional<std::pair<s32, s32>> IntegerSaturateBounds(Register::Size src_size,
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Register::Size dst_size,
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bool src_signed,
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bool dst_signed) {
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const u32 dst_bits = SizeInBits(dst_size);
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if (src_size == Register::Size::Word && dst_size == Register::Size::Word) {
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if (src_signed == dst_signed) {
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return std::nullopt;
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}
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return std::make_pair(0, std::numeric_limits<s32>::max());
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}
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if (dst_signed) {
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// Signed destination, clamp to [-128, 127] for instance
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return std::make_pair(-(1 << (dst_bits - 1)), (1 << (dst_bits - 1)) - 1);
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} else {
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// Unsigned destination
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if (dst_bits == 32) {
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// Avoid shifting by 32, that is undefined behavior
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return std::make_pair(0, s32(std::numeric_limits<u32>::max()));
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}
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return std::make_pair(0, (1 << dst_bits) - 1);
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}
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}
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2019-08-28 15:09:33 -04:00
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} // Anonymous namespace
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2019-01-30 00:09:40 -05:00
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u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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2018-12-20 17:09:21 -05:00
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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2018-12-15 15:32:51 -05:00
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switch (opcode->get().GetId()) {
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2019-04-15 19:04:33 -04:00
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case OpCode::Id::I2I_R:
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case OpCode::Id::I2I_C:
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case OpCode::Id::I2I_IMM: {
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2020-04-07 01:16:51 -04:00
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const bool src_signed = instr.conversion.is_input_signed;
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const bool dst_signed = instr.conversion.is_output_signed;
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const Register::Size src_size = instr.conversion.src_size;
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const Register::Size dst_size = instr.conversion.dst_size;
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const u32 selector = static_cast<u32>(instr.conversion.int_src.selector);
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2018-12-17 19:14:25 -05:00
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2020-04-07 01:16:51 -04:00
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Node value = [this, instr, opcode] {
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2019-04-15 19:04:33 -04:00
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switch (opcode->get().GetId()) {
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case OpCode::Id::I2I_R:
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return GetRegister(instr.gpr20);
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case OpCode::Id::I2I_C:
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset());
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case OpCode::Id::I2I_IMM:
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return Immediate(instr.alu.GetSignedImm20_20());
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default:
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UNREACHABLE();
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return Immediate(0);
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}
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}();
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2018-12-17 19:14:25 -05:00
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2020-04-07 01:16:51 -04:00
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// Ensure the source selector is valid
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switch (instr.conversion.src_size) {
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case Register::Size::Byte:
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break;
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case Register::Size::Short:
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ASSERT(selector == 0 || selector == 2);
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break;
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default:
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ASSERT(selector == 0);
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break;
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}
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if (src_size != Register::Size::Word || selector != 0) {
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value = SignedOperation(OperationCode::IBitfieldExtract, src_signed, std::move(value),
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Immediate(selector * 8), Immediate(SizeInBits(src_size)));
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}
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value = GetOperandAbsNegInteger(std::move(value), instr.conversion.abs_a,
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instr.conversion.negate_a, src_signed);
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if (instr.alu.saturate_d) {
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if (src_signed && !dst_signed) {
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Node is_negative = Operation(OperationCode::LogicalUGreaterEqual, value,
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Immediate(1 << (SizeInBits(src_size) - 1)));
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value = Operation(OperationCode::Select, std::move(is_negative), Immediate(0),
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std::move(value));
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// Simplify generated expressions, this can be removed without semantic impact
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SetTemporary(bb, 0, std::move(value));
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value = GetTemporary(0);
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if (dst_size != Register::Size::Word) {
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const Node limit = Immediate((1 << SizeInBits(dst_size)) - 1);
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Node is_large =
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Operation(OperationCode::LogicalUGreaterThan, std::move(value), limit);
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value = Operation(OperationCode::Select, std::move(is_large), limit,
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std::move(value));
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}
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} else if (const std::optional bounds =
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IntegerSaturateBounds(src_size, dst_size, src_signed, dst_signed)) {
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value = SignedOperation(OperationCode::IMax, src_signed, std::move(value),
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Immediate(bounds->first));
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value = SignedOperation(OperationCode::IMin, src_signed, std::move(value),
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Immediate(bounds->second));
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}
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} else if (dst_size != Register::Size::Word) {
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// No saturation, we only have to mask the result
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Node mask = Immediate((1 << SizeInBits(dst_size)) - 1);
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value = Operation(OperationCode::UBitwiseAnd, std::move(value), std::move(mask));
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2018-12-17 19:14:25 -05:00
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}
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2018-12-27 14:50:36 -05:00
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SetInternalFlagsFromInteger(bb, value, instr.generates_cc);
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2020-04-07 01:16:51 -04:00
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SetRegister(bb, instr.gpr0, std::move(value));
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2018-12-17 19:14:25 -05:00
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break;
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}
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2018-12-20 23:53:05 -05:00
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case OpCode::Id::I2F_R:
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2019-04-15 19:04:33 -04:00
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case OpCode::Id::I2F_C:
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case OpCode::Id::I2F_IMM: {
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2019-07-20 17:38:25 -04:00
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UNIMPLEMENTED_IF(instr.conversion.dst_size == Register::Size::Long);
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2018-12-20 23:53:05 -05:00
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in I2F is not implemented");
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2019-12-17 22:05:08 -05:00
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Node value = [&] {
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2019-04-15 19:04:33 -04:00
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switch (opcode->get().GetId()) {
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case OpCode::Id::I2F_R:
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2018-12-20 23:53:05 -05:00
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return GetRegister(instr.gpr20);
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2019-04-15 19:04:33 -04:00
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case OpCode::Id::I2F_C:
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2019-01-28 16:11:23 -05:00
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset());
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2019-04-15 19:04:33 -04:00
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case OpCode::Id::I2F_IMM:
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return Immediate(instr.alu.GetSignedImm20_20());
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default:
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UNREACHABLE();
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return Immediate(0);
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2018-12-20 23:53:05 -05:00
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}
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}();
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2019-12-17 22:05:08 -05:00
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2018-12-20 23:53:05 -05:00
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const bool input_signed = instr.conversion.is_input_signed;
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2019-12-17 22:05:08 -05:00
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2020-02-18 23:10:26 -05:00
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if (const u32 offset = static_cast<u32>(instr.conversion.int_src.selector); offset > 0) {
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2020-02-18 22:54:37 -05:00
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ASSERT(instr.conversion.src_size == Register::Size::Byte ||
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instr.conversion.src_size == Register::Size::Short);
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2020-02-18 23:40:35 -05:00
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if (instr.conversion.src_size == Register::Size::Short) {
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ASSERT(offset == 0 || offset == 2);
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}
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2020-02-18 22:54:37 -05:00
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value = SignedOperation(OperationCode::ILogicalShiftRight, input_signed,
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std::move(value), Immediate(offset * 8));
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2019-12-17 22:05:08 -05:00
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}
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2020-02-18 23:02:59 -05:00
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2018-12-20 23:53:05 -05:00
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value = ConvertIntegerSize(value, instr.conversion.src_size, input_signed);
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value = GetOperandAbsNegInteger(value, instr.conversion.abs_a, false, input_signed);
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value = SignedOperation(OperationCode::FCastInteger, input_signed, PRECISE, value);
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value = GetOperandAbsNegFloat(value, false, instr.conversion.negate_a);
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2018-12-27 14:50:36 -05:00
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SetInternalFlagsFromFloat(bb, value, instr.generates_cc);
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2019-07-20 17:38:25 -04:00
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if (instr.conversion.dst_size == Register::Size::Short) {
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value = Operation(OperationCode::HCastFloat, PRECISE, value);
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}
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2018-12-20 23:53:05 -05:00
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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2018-12-17 19:42:59 -05:00
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case OpCode::Id::F2F_R:
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2019-04-15 19:04:33 -04:00
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case OpCode::Id::F2F_C:
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case OpCode::Id::F2F_IMM: {
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2019-07-20 17:38:25 -04:00
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UNIMPLEMENTED_IF(instr.conversion.dst_size == Register::Size::Long);
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UNIMPLEMENTED_IF(instr.conversion.src_size == Register::Size::Long);
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2018-12-15 15:32:51 -05:00
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in F2F is not implemented");
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2018-12-17 19:42:59 -05:00
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Node value = [&]() {
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2019-04-15 19:04:33 -04:00
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switch (opcode->get().GetId()) {
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case OpCode::Id::F2F_R:
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2018-12-17 19:42:59 -05:00
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return GetRegister(instr.gpr20);
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2019-04-15 19:04:33 -04:00
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case OpCode::Id::F2F_C:
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2019-01-28 16:11:23 -05:00
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset());
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2019-04-15 19:04:33 -04:00
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case OpCode::Id::F2F_IMM:
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return GetImmediate19(instr);
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default:
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UNREACHABLE();
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return Immediate(0);
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2018-12-17 19:42:59 -05:00
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}
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}();
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2019-07-20 17:38:25 -04:00
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if (instr.conversion.src_size == Register::Size::Short) {
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2019-08-28 15:09:33 -04:00
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value = Operation(GetFloatSelector(instr.conversion.float_src.selector), NO_PRECISE,
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std::move(value));
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} else {
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ASSERT(instr.conversion.float_src.selector == 0);
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2019-07-20 17:38:25 -04:00
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}
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2018-12-15 15:32:51 -05:00
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value = GetOperandAbsNegFloat(value, instr.conversion.abs_a, instr.conversion.negate_a);
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2020-03-26 00:58:49 -04:00
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value = [&] {
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if (instr.conversion.src_size != instr.conversion.dst_size) {
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// Rounding operations only matter when the source and destination conversion size
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// is the same.
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return value;
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}
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2019-04-15 19:04:33 -04:00
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switch (instr.conversion.f2f.GetRoundingMode()) {
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2018-12-15 15:32:51 -05:00
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case Tegra::Shader::F2fRoundingOp::None:
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return value;
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case Tegra::Shader::F2fRoundingOp::Round:
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2020-03-26 00:58:49 -04:00
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return Operation(OperationCode::FRoundEven, value);
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2018-12-15 15:32:51 -05:00
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case Tegra::Shader::F2fRoundingOp::Floor:
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2020-03-26 00:58:49 -04:00
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return Operation(OperationCode::FFloor, value);
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2018-12-15 15:32:51 -05:00
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case Tegra::Shader::F2fRoundingOp::Ceil:
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2020-03-26 00:58:49 -04:00
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return Operation(OperationCode::FCeil, value);
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2018-12-15 15:32:51 -05:00
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case Tegra::Shader::F2fRoundingOp::Trunc:
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2020-03-26 00:58:49 -04:00
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return Operation(OperationCode::FTrunc, value);
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2019-04-03 03:33:36 -04:00
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default:
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UNIMPLEMENTED_MSG("Unimplemented F2F rounding mode {}",
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static_cast<u32>(instr.conversion.f2f.rounding.Value()));
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2019-07-20 17:38:25 -04:00
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return value;
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2018-12-15 15:32:51 -05:00
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}
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}();
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value = GetSaturatedFloat(value, instr.alu.saturate_d);
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2018-12-27 14:50:36 -05:00
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SetInternalFlagsFromFloat(bb, value, instr.generates_cc);
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2019-07-20 17:38:25 -04:00
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if (instr.conversion.dst_size == Register::Size::Short) {
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value = Operation(OperationCode::HCastFloat, PRECISE, value);
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}
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2018-12-15 15:32:51 -05:00
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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2018-12-20 23:57:13 -05:00
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case OpCode::Id::F2I_R:
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2019-04-15 19:04:33 -04:00
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case OpCode::Id::F2I_C:
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case OpCode::Id::F2I_IMM: {
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2019-07-20 17:38:25 -04:00
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UNIMPLEMENTED_IF(instr.conversion.src_size == Register::Size::Long);
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2018-12-20 23:57:13 -05:00
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in F2I is not implemented");
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Node value = [&]() {
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2019-04-15 19:04:33 -04:00
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switch (opcode->get().GetId()) {
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case OpCode::Id::F2I_R:
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2018-12-20 23:57:13 -05:00
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return GetRegister(instr.gpr20);
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2019-04-15 19:04:33 -04:00
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case OpCode::Id::F2I_C:
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2019-01-28 16:11:23 -05:00
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset());
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2019-04-15 19:04:33 -04:00
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case OpCode::Id::F2I_IMM:
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return GetImmediate19(instr);
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default:
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UNREACHABLE();
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return Immediate(0);
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2018-12-20 23:57:13 -05:00
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}
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}();
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2019-07-20 17:38:25 -04:00
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if (instr.conversion.src_size == Register::Size::Short) {
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2019-08-28 15:09:33 -04:00
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value = Operation(GetFloatSelector(instr.conversion.float_src.selector), NO_PRECISE,
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std::move(value));
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} else {
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ASSERT(instr.conversion.float_src.selector == 0);
|
2019-07-20 17:38:25 -04:00
|
|
|
}
|
|
|
|
|
2018-12-20 23:57:13 -05:00
|
|
|
value = GetOperandAbsNegFloat(value, instr.conversion.abs_a, instr.conversion.negate_a);
|
|
|
|
|
|
|
|
value = [&]() {
|
|
|
|
switch (instr.conversion.f2i.rounding) {
|
2019-02-11 17:46:45 -05:00
|
|
|
case Tegra::Shader::F2iRoundingOp::RoundEven:
|
|
|
|
return Operation(OperationCode::FRoundEven, PRECISE, value);
|
2018-12-20 23:57:13 -05:00
|
|
|
case Tegra::Shader::F2iRoundingOp::Floor:
|
|
|
|
return Operation(OperationCode::FFloor, PRECISE, value);
|
|
|
|
case Tegra::Shader::F2iRoundingOp::Ceil:
|
|
|
|
return Operation(OperationCode::FCeil, PRECISE, value);
|
|
|
|
case Tegra::Shader::F2iRoundingOp::Trunc:
|
|
|
|
return Operation(OperationCode::FTrunc, PRECISE, value);
|
|
|
|
default:
|
|
|
|
UNIMPLEMENTED_MSG("Unimplemented F2I rounding mode {}",
|
|
|
|
static_cast<u32>(instr.conversion.f2i.rounding.Value()));
|
2018-12-21 16:47:22 -05:00
|
|
|
return Immediate(0);
|
2018-12-20 23:57:13 -05:00
|
|
|
}
|
|
|
|
}();
|
|
|
|
const bool is_signed = instr.conversion.is_output_signed;
|
|
|
|
value = SignedOperation(OperationCode::ICastFloat, is_signed, PRECISE, value);
|
2019-04-15 19:04:33 -04:00
|
|
|
value = ConvertIntegerSize(value, instr.conversion.dst_size, is_signed);
|
2018-12-20 23:57:13 -05:00
|
|
|
|
|
|
|
SetRegister(bb, instr.gpr0, value);
|
|
|
|
break;
|
|
|
|
}
|
2018-12-15 15:32:51 -05:00
|
|
|
default:
|
|
|
|
UNIMPLEMENTED_MSG("Unhandled conversion instruction: {}", opcode->get().GetName());
|
|
|
|
}
|
2018-12-20 17:09:21 -05:00
|
|
|
|
|
|
|
return pc;
|
|
|
|
}
|
|
|
|
|
2019-02-11 17:46:45 -05:00
|
|
|
} // namespace VideoCommon::Shader
|