2021-05-05 01:19:08 -04:00
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <string_view>
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#include "shader_recompiler/backend/glasm/emit_context.h"
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#include "shader_recompiler/backend/glasm/emit_glasm_instructions.h"
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#include "shader_recompiler/frontend/ir/program.h"
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#include "shader_recompiler/frontend/ir/value.h"
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#ifdef _MSC_VER
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#pragma warning(disable : 4100)
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#endif
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namespace Shader::Backend::GLASM {
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#define NotImplemented() throw NotImplementedException("GLASM instruction {}", __LINE__)
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void EmitPhi(EmitContext& ctx, IR::Inst& inst) {
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NotImplemented();
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}
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void EmitVoid(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitBranch(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitBranchConditional(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitLoopMerge(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitSelectionMerge(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitReturn(EmitContext& ctx) {
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ctx.Add("RET;");
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}
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void EmitJoin(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitUnreachable(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitDemoteToHelperInvocation(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitBarrier(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitWorkgroupMemoryBarrier(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitDeviceMemoryBarrier(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitPrologue(EmitContext& ctx) {
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// TODO
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}
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void EmitEpilogue(EmitContext& ctx) {
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// TODO
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}
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void EmitEmitVertex(EmitContext& ctx, const IR::Value& stream) {
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NotImplemented();
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}
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void EmitEndPrimitive(EmitContext& ctx, const IR::Value& stream) {
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NotImplemented();
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}
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void EmitGetRegister(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitSetRegister(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetPred(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitSetPred(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitSetGotoVariable(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetGotoVariable(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitSetIndirectBranchVariable(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetIndirectBranchVariable(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetZFlag(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetSFlag(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetCFlag(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetOFlag(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitSetZFlag(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitSetSFlag(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitSetCFlag(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitSetOFlag(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitWorkgroupId(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitLocalInvocationId(EmitContext& ctx, IR::Inst& inst) {
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ctx.Add("MOV.S {},invocation.localid;", inst);
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}
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void EmitInvocationId(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitSampleId(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitIsHelperInvocation(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitYDirection(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitLoadLocal(EmitContext& ctx, ScalarU32 word_offset) {
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NotImplemented();
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}
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void EmitWriteLocal(EmitContext& ctx, ScalarU32 word_offset, ScalarU32 value) {
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NotImplemented();
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}
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void EmitUndefU1(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitUndefU8(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitUndefU16(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitUndefU32(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitUndefU64(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitLoadSharedU8(EmitContext& ctx, ScalarU32 offset) {
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NotImplemented();
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}
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void EmitLoadSharedS8(EmitContext& ctx, ScalarU32 offset) {
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NotImplemented();
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}
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void EmitLoadSharedU16(EmitContext& ctx, ScalarU32 offset) {
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NotImplemented();
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}
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void EmitLoadSharedS16(EmitContext& ctx, ScalarU32 offset) {
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NotImplemented();
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}
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void EmitLoadSharedU32(EmitContext& ctx, ScalarU32 offset) {
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NotImplemented();
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}
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void EmitLoadSharedU64(EmitContext& ctx, ScalarU32 offset) {
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NotImplemented();
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}
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void EmitLoadSharedU128(EmitContext& ctx, ScalarU32 offset) {
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NotImplemented();
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}
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void EmitWriteSharedU8(EmitContext& ctx, ScalarU32 offset, ScalarU32 value) {
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NotImplemented();
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}
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void EmitWriteSharedU16(EmitContext& ctx, ScalarU32 offset, ScalarU32 value) {
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NotImplemented();
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}
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void EmitWriteSharedU32(EmitContext& ctx, ScalarU32 offset, ScalarU32 value) {
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NotImplemented();
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}
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void EmitWriteSharedU64(EmitContext& ctx, ScalarU32 offset, Register value) {
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NotImplemented();
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}
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void EmitWriteSharedU128(EmitContext& ctx, ScalarU32 offset, Register value) {
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NotImplemented();
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}
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void EmitGetZeroFromOp(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetSignFromOp(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetCarryFromOp(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetOverflowFromOp(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetSparseFromOp(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetInBoundsFromOp(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitSharedAtomicIAdd32(EmitContext& ctx, ScalarU32 pointer_offset, ScalarU32 value) {
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NotImplemented();
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}
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void EmitSharedAtomicSMin32(EmitContext& ctx, ScalarU32 pointer_offset, ScalarS32 value) {
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NotImplemented();
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}
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void EmitSharedAtomicUMin32(EmitContext& ctx, ScalarU32 pointer_offset, ScalarU32 value) {
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NotImplemented();
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}
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void EmitSharedAtomicSMax32(EmitContext& ctx, ScalarU32 pointer_offset, ScalarS32 value) {
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NotImplemented();
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}
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void EmitSharedAtomicUMax32(EmitContext& ctx, ScalarU32 pointer_offset, ScalarU32 value) {
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NotImplemented();
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}
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void EmitSharedAtomicInc32(EmitContext& ctx, ScalarU32 pointer_offset, ScalarU32 value) {
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NotImplemented();
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}
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void EmitSharedAtomicDec32(EmitContext& ctx, ScalarU32 pointer_offset, ScalarU32 value) {
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NotImplemented();
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}
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void EmitSharedAtomicAnd32(EmitContext& ctx, ScalarU32 pointer_offset, ScalarU32 value) {
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NotImplemented();
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}
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void EmitSharedAtomicOr32(EmitContext& ctx, ScalarU32 pointer_offset, ScalarU32 value) {
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NotImplemented();
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}
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void EmitSharedAtomicXor32(EmitContext& ctx, ScalarU32 pointer_offset, ScalarU32 value) {
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NotImplemented();
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}
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void EmitSharedAtomicExchange32(EmitContext& ctx, ScalarU32 pointer_offset, ScalarU32 value) {
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NotImplemented();
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}
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void EmitSharedAtomicExchange64(EmitContext& ctx, ScalarU32 pointer_offset, Register value) {
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NotImplemented();
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}
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void EmitStorageAtomicIAdd32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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ScalarU32 value) {
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NotImplemented();
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}
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void EmitStorageAtomicSMin32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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ScalarS32 value) {
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NotImplemented();
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}
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void EmitStorageAtomicUMin32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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ScalarU32 value) {
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NotImplemented();
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}
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void EmitStorageAtomicSMax32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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ScalarS32 value) {
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NotImplemented();
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}
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|
|
void EmitStorageAtomicUMax32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
2021-05-09 02:11:34 -04:00
|
|
|
ScalarU32 value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitStorageAtomicInc32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
2021-05-09 02:11:34 -04:00
|
|
|
ScalarU32 value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitStorageAtomicDec32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
2021-05-09 02:11:34 -04:00
|
|
|
ScalarU32 value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitStorageAtomicAnd32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
2021-05-09 02:11:34 -04:00
|
|
|
ScalarU32 value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitStorageAtomicOr32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
2021-05-09 02:11:34 -04:00
|
|
|
ScalarU32 value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitStorageAtomicXor32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
2021-05-09 02:11:34 -04:00
|
|
|
ScalarU32 value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitStorageAtomicExchange32(EmitContext& ctx, const IR::Value& binding,
|
2021-05-09 02:11:34 -04:00
|
|
|
const IR::Value& offset, ScalarU32 value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitStorageAtomicIAdd64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitStorageAtomicSMin64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitStorageAtomicUMin64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitStorageAtomicSMax64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitStorageAtomicUMax64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitStorageAtomicAnd64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitStorageAtomicOr64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitStorageAtomicXor64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitStorageAtomicExchange64(EmitContext& ctx, const IR::Value& binding,
|
2021-05-09 02:11:34 -04:00
|
|
|
const IR::Value& offset, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitStorageAtomicAddF32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
2021-05-09 02:11:34 -04:00
|
|
|
ScalarF32 value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitStorageAtomicAddF16x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitStorageAtomicAddF32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitStorageAtomicMinF16x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitStorageAtomicMinF32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitStorageAtomicMaxF16x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitStorageAtomicMaxF32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicIAdd32(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicSMin32(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicUMin32(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicSMax32(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicUMax32(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicInc32(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicDec32(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicAnd32(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicOr32(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicXor32(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicExchange32(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicIAdd64(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicSMin64(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicUMin64(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicSMax64(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicUMax64(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicInc64(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicDec64(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicAnd64(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicOr64(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicXor64(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicExchange64(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicAddF32(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicAddF16x2(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicAddF32x2(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicMinF16x2(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicMinF32x2(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicMaxF16x2(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitGlobalAtomicMaxF32x2(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitLogicalOr(EmitContext& ctx, ScalarS32 a, ScalarS32 b) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitLogicalAnd(EmitContext& ctx, ScalarS32 a, ScalarS32 b) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitLogicalXor(EmitContext& ctx, ScalarS32 a, ScalarS32 b) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitLogicalNot(EmitContext& ctx, ScalarS32 value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertS16F16(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertS16F32(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertS16F64(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertS32F16(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertS32F32(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertS32F64(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertS64F16(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertS64F32(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertS64F64(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertU16F16(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertU16F32(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertU16F64(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertU32F16(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertU32F32(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertU32F64(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertU64F16(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertU64F32(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertU64F64(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertU64U32(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertU32U64(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF16F32(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF32F16(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF32F64(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF64F32(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF16S8(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF16S16(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF16S32(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF16S64(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF16U8(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF16U16(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF16U32(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF16U64(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF32S8(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF32S16(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF32S32(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF32S64(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF32U8(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF32U16(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF32U32(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF32U64(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF64S8(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF64S16(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF64S32(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF64S64(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF64U8(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF64U16(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF64U32(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitConvertF64U64(EmitContext& ctx, Register value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageSampleImplicitLod(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageSampleExplicitLod(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageSampleDrefImplicitLod(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageSampleDrefExplicitLod(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageGather(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageGatherDref(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageFetch(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageQueryDimensions(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageQueryLod(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageGradient(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageRead(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageWrite(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageSampleImplicitLod(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageSampleExplicitLod(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageSampleDrefImplicitLod(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageSampleDrefExplicitLod(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageGather(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageGatherDref(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageFetch(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageQueryDimensions(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageQueryLod(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageGradient(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageRead(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageWrite(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-08 15:28:52 -04:00
|
|
|
void EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register coords, Register bias_lc, const IR::Value& offset) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-08 15:28:52 -04:00
|
|
|
void EmitImageSampleExplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register coords, Register lod_lc, const IR::Value& offset) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-08 15:28:52 -04:00
|
|
|
void EmitImageSampleDrefImplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register coords, Register dref, Register bias_lc,
|
|
|
|
const IR::Value& offset) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-08 15:28:52 -04:00
|
|
|
void EmitImageSampleDrefExplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register coords, Register dref, Register lod_lc,
|
|
|
|
const IR::Value& offset) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitImageGather(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coords,
|
|
|
|
const IR::Value& offset, const IR::Value& offset2) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitImageGatherDref(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coords,
|
|
|
|
const IR::Value& offset, const IR::Value& offset2, Register dref) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitImageFetch(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coords,
|
|
|
|
Register offset, Register lod, Register ms) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-08 15:28:52 -04:00
|
|
|
void EmitImageQueryDimensions(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register lod) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitImageQueryLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coords) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitImageGradient(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coords,
|
|
|
|
Register derivates, Register offset, Register lod_clamp) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitImageRead(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coords) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitImageWrite(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coords,
|
|
|
|
Register color) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageAtomicIAdd32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageAtomicSMin32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageAtomicUMin32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageAtomicSMax32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageAtomicUMax32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageAtomicInc32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageAtomicDec32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageAtomicAnd32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageAtomicOr32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageAtomicXor32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageAtomicExchange32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageAtomicIAdd32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageAtomicSMin32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageAtomicUMin32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageAtomicSMax32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageAtomicUMax32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageAtomicInc32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageAtomicDec32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageAtomicAnd32(EmitContext&) {
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NotImplemented();
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}
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void EmitBoundImageAtomicOr32(EmitContext&) {
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NotImplemented();
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}
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void EmitBoundImageAtomicXor32(EmitContext&) {
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NotImplemented();
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}
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void EmitBoundImageAtomicExchange32(EmitContext&) {
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NotImplemented();
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}
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2021-05-08 15:28:52 -04:00
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void EmitImageAtomicIAdd32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
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2021-05-09 02:11:34 -04:00
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Register coords, ScalarU32 value) {
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2021-05-05 01:19:08 -04:00
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NotImplemented();
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}
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2021-05-08 15:28:52 -04:00
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void EmitImageAtomicSMin32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
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2021-05-09 02:11:34 -04:00
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Register coords, ScalarS32 value) {
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2021-05-05 01:19:08 -04:00
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NotImplemented();
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}
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2021-05-08 15:28:52 -04:00
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void EmitImageAtomicUMin32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
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2021-05-09 02:11:34 -04:00
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Register coords, ScalarU32 value) {
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2021-05-05 01:19:08 -04:00
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NotImplemented();
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}
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2021-05-08 15:28:52 -04:00
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void EmitImageAtomicSMax32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
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2021-05-09 02:11:34 -04:00
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Register coords, ScalarS32 value) {
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2021-05-05 01:19:08 -04:00
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NotImplemented();
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}
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2021-05-08 15:28:52 -04:00
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void EmitImageAtomicUMax32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
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2021-05-09 02:11:34 -04:00
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Register coords, ScalarU32 value) {
|
2021-05-05 01:19:08 -04:00
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NotImplemented();
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}
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2021-05-09 02:11:34 -04:00
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void EmitImageAtomicInc32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coords,
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ScalarU32 value) {
|
2021-05-05 01:19:08 -04:00
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NotImplemented();
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}
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2021-05-09 02:11:34 -04:00
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void EmitImageAtomicDec32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coords,
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ScalarU32 value) {
|
2021-05-05 01:19:08 -04:00
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NotImplemented();
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}
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2021-05-09 02:11:34 -04:00
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void EmitImageAtomicAnd32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coords,
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|
ScalarU32 value) {
|
2021-05-05 01:19:08 -04:00
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|
NotImplemented();
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|
}
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|
2021-05-09 02:11:34 -04:00
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void EmitImageAtomicOr32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coords,
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|
ScalarU32 value) {
|
2021-05-05 01:19:08 -04:00
|
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|
NotImplemented();
|
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|
}
|
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|
2021-05-09 02:11:34 -04:00
|
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|
void EmitImageAtomicXor32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coords,
|
|
|
|
ScalarU32 value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
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|
|
|
2021-05-08 15:28:52 -04:00
|
|
|
void EmitImageAtomicExchange32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register coords, ScalarU32 value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
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|
|
void EmitLaneId(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
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|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitVoteAll(EmitContext& ctx, ScalarS32 pred) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
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|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitVoteAny(EmitContext& ctx, ScalarS32 pred) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitVoteEqual(EmitContext& ctx, ScalarS32 pred) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitSubgroupBallot(EmitContext& ctx, ScalarS32 pred) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitSubgroupEqMask(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitSubgroupLtMask(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitSubgroupLeMask(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitSubgroupGtMask(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitSubgroupGeMask(EmitContext& ctx) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitShuffleIndex(EmitContext& ctx, IR::Inst& inst, ScalarU32 value, ScalarU32 index,
|
|
|
|
ScalarU32 clamp, ScalarU32 segmentation_mask) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitShuffleUp(EmitContext& ctx, IR::Inst& inst, ScalarU32 value, ScalarU32 index,
|
|
|
|
ScalarU32 clamp, ScalarU32 segmentation_mask) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitShuffleDown(EmitContext& ctx, IR::Inst& inst, ScalarU32 value, ScalarU32 index,
|
|
|
|
ScalarU32 clamp, ScalarU32 segmentation_mask) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitShuffleButterfly(EmitContext& ctx, IR::Inst& inst, ScalarU32 value, ScalarU32 index,
|
|
|
|
ScalarU32 clamp, ScalarU32 segmentation_mask) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitFSwizzleAdd(EmitContext& ctx, ScalarF32 op_a, ScalarF32 op_b, ScalarU32 swizzle) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitDPdxFine(EmitContext& ctx, ScalarF32 op_a) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitDPdyFine(EmitContext& ctx, ScalarF32 op_a) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitDPdxCoarse(EmitContext& ctx, ScalarF32 op_a) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitDPdyCoarse(EmitContext& ctx, ScalarF32 op_a) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
} // namespace Shader::Backend::GLASM
|