2021-05-05 01:19:08 -04:00
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <string_view>
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#include "shader_recompiler/backend/glasm/emit_context.h"
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#include "shader_recompiler/backend/glasm/emit_glasm_instructions.h"
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#include "shader_recompiler/frontend/ir/program.h"
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#include "shader_recompiler/frontend/ir/value.h"
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#ifdef _MSC_VER
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#pragma warning(disable : 4100)
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#endif
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namespace Shader::Backend::GLASM {
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#define NotImplemented() throw NotImplementedException("GLASM instruction {}", __LINE__)
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void EmitPhi(EmitContext& ctx, IR::Inst& inst) {
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NotImplemented();
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}
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void EmitVoid(EmitContext&) {}
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void EmitBranch(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitBranchConditional(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitLoopMerge(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitSelectionMerge(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitReturn(EmitContext& ctx) {
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ctx.Add("RET;");
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}
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void EmitJoin(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitUnreachable(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitDemoteToHelperInvocation(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitBarrier(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitWorkgroupMemoryBarrier(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitDeviceMemoryBarrier(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitPrologue(EmitContext& ctx) {
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// TODO
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}
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void EmitEpilogue(EmitContext& ctx) {
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// TODO
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}
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void EmitEmitVertex(EmitContext& ctx, const IR::Value& stream) {
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NotImplemented();
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}
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void EmitEndPrimitive(EmitContext& ctx, const IR::Value& stream) {
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NotImplemented();
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}
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void EmitGetRegister(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitSetRegister(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetPred(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitSetPred(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitSetGotoVariable(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetGotoVariable(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitSetIndirectBranchVariable(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetIndirectBranchVariable(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetZFlag(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetSFlag(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetCFlag(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetOFlag(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitSetZFlag(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitSetSFlag(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitSetCFlag(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitSetOFlag(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitWorkgroupId(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitLocalInvocationId(EmitContext& ctx, IR::Inst& inst) {
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ctx.Add("MOV.S {},invocation.localid;", inst);
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}
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void EmitInvocationId(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitSampleId(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitIsHelperInvocation(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitYDirection(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitLoadLocal(EmitContext& ctx, ScalarU32 word_offset) {
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NotImplemented();
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}
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void EmitWriteLocal(EmitContext& ctx, ScalarU32 word_offset, ScalarU32 value) {
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NotImplemented();
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}
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void EmitUndefU1(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitUndefU8(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitUndefU16(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitUndefU32(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitUndefU64(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetZeroFromOp(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetSignFromOp(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetCarryFromOp(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetOverflowFromOp(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetSparseFromOp(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitGetInBoundsFromOp(EmitContext& ctx) {
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NotImplemented();
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}
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void EmitLogicalOr(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) {
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ctx.Add("OR.S {},{},{};", inst, a, b);
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}
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void EmitLogicalAnd(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) {
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ctx.Add("AND.S {},{},{};", inst, a, b);
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}
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void EmitLogicalXor(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b) {
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ctx.Add("XOR.S {},{},{};", inst, a, b);
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}
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void EmitLogicalNot(EmitContext& ctx, IR::Inst& inst, ScalarS32 value) {
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ctx.Add("SEQ.S {},{},0;", inst, value);
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}
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void EmitBindlessImageSampleImplicitLod(EmitContext&) {
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NotImplemented();
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}
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void EmitBindlessImageSampleExplicitLod(EmitContext&) {
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NotImplemented();
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}
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void EmitBindlessImageSampleDrefImplicitLod(EmitContext&) {
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NotImplemented();
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}
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void EmitBindlessImageSampleDrefExplicitLod(EmitContext&) {
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NotImplemented();
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}
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void EmitBindlessImageGather(EmitContext&) {
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NotImplemented();
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}
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void EmitBindlessImageGatherDref(EmitContext&) {
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NotImplemented();
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}
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void EmitBindlessImageFetch(EmitContext&) {
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NotImplemented();
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}
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void EmitBindlessImageQueryDimensions(EmitContext&) {
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NotImplemented();
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}
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void EmitBindlessImageQueryLod(EmitContext&) {
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NotImplemented();
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}
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void EmitBindlessImageGradient(EmitContext&) {
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NotImplemented();
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}
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void EmitBindlessImageRead(EmitContext&) {
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NotImplemented();
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}
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void EmitBindlessImageWrite(EmitContext&) {
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NotImplemented();
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}
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void EmitBoundImageSampleImplicitLod(EmitContext&) {
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NotImplemented();
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}
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void EmitBoundImageSampleExplicitLod(EmitContext&) {
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NotImplemented();
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}
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void EmitBoundImageSampleDrefImplicitLod(EmitContext&) {
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NotImplemented();
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}
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void EmitBoundImageSampleDrefExplicitLod(EmitContext&) {
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NotImplemented();
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}
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void EmitBoundImageGather(EmitContext&) {
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NotImplemented();
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}
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void EmitBoundImageGatherDref(EmitContext&) {
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NotImplemented();
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}
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void EmitBoundImageFetch(EmitContext&) {
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NotImplemented();
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}
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void EmitBoundImageQueryDimensions(EmitContext&) {
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NotImplemented();
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}
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void EmitBoundImageQueryLod(EmitContext&) {
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NotImplemented();
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}
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void EmitBoundImageGradient(EmitContext&) {
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NotImplemented();
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}
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void EmitBoundImageRead(EmitContext&) {
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NotImplemented();
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}
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void EmitBoundImageWrite(EmitContext&) {
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NotImplemented();
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}
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void EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
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Register coords, Register bias_lc, const IR::Value& offset) {
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NotImplemented();
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}
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void EmitImageSampleExplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
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Register coords, Register lod_lc, const IR::Value& offset) {
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NotImplemented();
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}
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2021-05-08 15:28:52 -04:00
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void EmitImageSampleDrefImplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
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Register coords, Register dref, Register bias_lc,
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const IR::Value& offset) {
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NotImplemented();
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}
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2021-05-08 15:28:52 -04:00
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void EmitImageSampleDrefExplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
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Register coords, Register dref, Register lod_lc,
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const IR::Value& offset) {
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NotImplemented();
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}
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void EmitImageGather(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coords,
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const IR::Value& offset, const IR::Value& offset2) {
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NotImplemented();
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}
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void EmitImageGatherDref(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coords,
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const IR::Value& offset, const IR::Value& offset2, Register dref) {
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NotImplemented();
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}
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void EmitImageFetch(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coords,
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|
Register offset, Register lod, Register ms) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-08 15:28:52 -04:00
|
|
|
void EmitImageQueryDimensions(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register lod) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
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|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitImageQueryLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coords) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitImageGradient(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coords,
|
|
|
|
Register derivates, Register offset, Register lod_clamp) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
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|
2021-05-09 02:11:34 -04:00
|
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|
void EmitImageRead(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coords) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
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|
2021-05-09 02:11:34 -04:00
|
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|
void EmitImageWrite(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coords,
|
|
|
|
Register color) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageAtomicIAdd32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageAtomicSMin32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageAtomicUMin32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageAtomicSMax32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageAtomicUMax32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageAtomicInc32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageAtomicDec32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageAtomicAnd32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageAtomicOr32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageAtomicXor32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBindlessImageAtomicExchange32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageAtomicIAdd32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageAtomicSMin32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageAtomicUMin32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageAtomicSMax32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageAtomicUMax32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageAtomicInc32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageAtomicDec32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageAtomicAnd32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageAtomicOr32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageAtomicXor32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
void EmitBoundImageAtomicExchange32(EmitContext&) {
|
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-08 15:28:52 -04:00
|
|
|
void EmitImageAtomicIAdd32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register coords, ScalarU32 value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-08 15:28:52 -04:00
|
|
|
void EmitImageAtomicSMin32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register coords, ScalarS32 value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-08 15:28:52 -04:00
|
|
|
void EmitImageAtomicUMin32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register coords, ScalarU32 value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-08 15:28:52 -04:00
|
|
|
void EmitImageAtomicSMax32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register coords, ScalarS32 value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-08 15:28:52 -04:00
|
|
|
void EmitImageAtomicUMax32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register coords, ScalarU32 value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitImageAtomicInc32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coords,
|
|
|
|
ScalarU32 value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitImageAtomicDec32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coords,
|
|
|
|
ScalarU32 value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitImageAtomicAnd32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coords,
|
|
|
|
ScalarU32 value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitImageAtomicOr32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coords,
|
|
|
|
ScalarU32 value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-09 02:11:34 -04:00
|
|
|
void EmitImageAtomicXor32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coords,
|
|
|
|
ScalarU32 value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
2021-05-08 15:28:52 -04:00
|
|
|
void EmitImageAtomicExchange32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
2021-05-09 02:11:34 -04:00
|
|
|
Register coords, ScalarU32 value) {
|
2021-05-05 01:19:08 -04:00
|
|
|
NotImplemented();
|
|
|
|
}
|
|
|
|
|
|
|
|
} // namespace Shader::Backend::GLASM
|