2019-04-27 01:07:18 -04:00
|
|
|
// Copyright 2019 yuzu Emulator Project
|
|
|
|
// Licensed under GPLv2 or any later version
|
|
|
|
// Refer to the license.txt file included.
|
|
|
|
|
|
|
|
#include <algorithm>
|
2019-06-08 11:25:11 -04:00
|
|
|
#include <vector>
|
|
|
|
#include <fmt/format.h>
|
2019-04-27 01:07:18 -04:00
|
|
|
|
|
|
|
#include "common/assert.h"
|
2019-06-08 11:25:11 -04:00
|
|
|
#include "common/bit_field.h"
|
2019-04-27 01:07:18 -04:00
|
|
|
#include "common/common_types.h"
|
2019-06-08 11:25:11 -04:00
|
|
|
#include "common/logging/log.h"
|
2019-04-27 01:07:18 -04:00
|
|
|
#include "video_core/engines/shader_bytecode.h"
|
2019-06-08 11:25:11 -04:00
|
|
|
#include "video_core/shader/node_helper.h"
|
2019-04-27 01:07:18 -04:00
|
|
|
#include "video_core/shader/shader_ir.h"
|
|
|
|
|
|
|
|
namespace VideoCommon::Shader {
|
|
|
|
|
|
|
|
using Tegra::Shader::Instruction;
|
|
|
|
using Tegra::Shader::OpCode;
|
2020-03-11 08:19:56 -04:00
|
|
|
using Tegra::Shader::PredCondition;
|
2020-03-11 10:11:11 -04:00
|
|
|
using Tegra::Shader::StoreType;
|
2019-04-27 01:07:18 -04:00
|
|
|
|
|
|
|
namespace {
|
|
|
|
std::size_t GetImageTypeNumCoordinates(Tegra::Shader::ImageType image_type) {
|
|
|
|
switch (image_type) {
|
|
|
|
case Tegra::Shader::ImageType::Texture1D:
|
|
|
|
case Tegra::Shader::ImageType::TextureBuffer:
|
|
|
|
return 1;
|
|
|
|
case Tegra::Shader::ImageType::Texture1DArray:
|
|
|
|
case Tegra::Shader::ImageType::Texture2D:
|
|
|
|
return 2;
|
|
|
|
case Tegra::Shader::ImageType::Texture2DArray:
|
|
|
|
case Tegra::Shader::ImageType::Texture3D:
|
|
|
|
return 3;
|
|
|
|
}
|
|
|
|
UNREACHABLE();
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
} // Anonymous namespace
|
|
|
|
|
|
|
|
u32 ShaderIR::DecodeImage(NodeBlock& bb, u32 pc) {
|
|
|
|
const Instruction instr = {program_code[pc]};
|
|
|
|
const auto opcode = OpCode::Decode(instr);
|
|
|
|
|
2019-09-18 00:07:01 -04:00
|
|
|
const auto GetCoordinates = [this, instr](Tegra::Shader::ImageType image_type) {
|
|
|
|
std::vector<Node> coords;
|
|
|
|
const std::size_t num_coords{GetImageTypeNumCoordinates(image_type)};
|
|
|
|
coords.reserve(num_coords);
|
|
|
|
for (std::size_t i = 0; i < num_coords; ++i) {
|
|
|
|
coords.push_back(GetRegister(instr.gpr8.Value() + i));
|
|
|
|
}
|
|
|
|
return coords;
|
|
|
|
};
|
|
|
|
|
2019-04-27 01:07:18 -04:00
|
|
|
switch (opcode->get().GetId()) {
|
2019-09-18 00:07:01 -04:00
|
|
|
case OpCode::Id::SULD: {
|
|
|
|
UNIMPLEMENTED_IF(instr.suldst.out_of_bounds_store !=
|
|
|
|
Tegra::Shader::OutOfBoundsStore::Ignore);
|
|
|
|
|
|
|
|
const auto type{instr.suldst.image_type};
|
|
|
|
auto& image{instr.suldst.is_immediate ? GetImage(instr.image, type)
|
|
|
|
: GetBindlessImage(instr.gpr39, type)};
|
|
|
|
image.MarkRead();
|
|
|
|
|
2020-03-09 08:33:26 -04:00
|
|
|
if (instr.suldst.mode == Tegra::Shader::SurfaceDataMode::P) {
|
|
|
|
u32 indexer = 0;
|
|
|
|
for (u32 element = 0; element < 4; ++element) {
|
|
|
|
if (!instr.suldst.IsComponentEnabled(element)) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
MetaImage meta{image, {}, element};
|
|
|
|
Node value = Operation(OperationCode::ImageLoad, meta, GetCoordinates(type));
|
|
|
|
SetTemporary(bb, indexer++, std::move(value));
|
|
|
|
}
|
|
|
|
for (u32 i = 0; i < indexer; ++i) {
|
|
|
|
SetRegister(bb, instr.gpr0.Value() + i, GetTemporary(i));
|
|
|
|
}
|
|
|
|
} else if (instr.suldst.mode == Tegra::Shader::SurfaceDataMode::D_BA) {
|
|
|
|
UNIMPLEMENTED_IF(instr.suldst.GetStoreDataLayout() != StoreType::Bits32);
|
|
|
|
|
|
|
|
switch (instr.suldst.GetStoreDataLayout()) {
|
|
|
|
case StoreType::Bits32: {
|
2020-03-11 07:15:31 -04:00
|
|
|
Node value{};
|
|
|
|
for (s32 i = 3; i >= 0; i--) {
|
|
|
|
MetaImage meta{image, {}, i};
|
|
|
|
Node element_value =
|
|
|
|
Operation(OperationCode::ImageLoad, meta, GetCoordinates(type));
|
|
|
|
|
|
|
|
const Node comp = GetPredicateComparisonFloat(PredCondition::GreaterEqual,
|
|
|
|
element_value, Immediate(1.0f));
|
|
|
|
const Node mul =
|
|
|
|
Operation(OperationCode::Select, comp, Immediate(1.f), Immediate(255.f));
|
|
|
|
|
|
|
|
Node element = Operation(OperationCode::FMul, NO_PRECISE, element_value, mul);
|
|
|
|
element = SignedOperation(OperationCode::ICastFloat, true, NO_PRECISE,
|
|
|
|
std::move(element));
|
|
|
|
element = Operation(OperationCode::ULogicalShiftLeft, std::move(element),
|
|
|
|
Immediate(8 * i));
|
|
|
|
if (i == 3) {
|
|
|
|
//(namkazt) for now i'm force it to 0 at alpha component if color is in
|
|
|
|
// range (0-255)
|
|
|
|
value = Operation(OperationCode::Select, comp, Immediate(0),
|
|
|
|
std::move(element));
|
|
|
|
} else {
|
|
|
|
value = Operation(OperationCode::UBitwiseOr, value,
|
|
|
|
Operation(OperationCode::Select, comp,
|
|
|
|
std::move(element_value), std::move(element)));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
SetRegister(bb, instr.gpr0.Value(), std::move(value));
|
2020-03-09 08:33:26 -04:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
UNREACHABLE();
|
|
|
|
break;
|
2019-09-18 00:07:01 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2019-04-27 01:07:18 -04:00
|
|
|
case OpCode::Id::SUST: {
|
2019-09-18 00:07:01 -04:00
|
|
|
UNIMPLEMENTED_IF(instr.suldst.mode != Tegra::Shader::SurfaceDataMode::P);
|
|
|
|
UNIMPLEMENTED_IF(instr.suldst.out_of_bounds_store !=
|
|
|
|
Tegra::Shader::OutOfBoundsStore::Ignore);
|
|
|
|
UNIMPLEMENTED_IF(instr.suldst.component_mask_selector != 0xf); // Ensure we have RGBA
|
2019-04-27 01:07:18 -04:00
|
|
|
|
|
|
|
std::vector<Node> values;
|
|
|
|
constexpr std::size_t hardcoded_size{4};
|
|
|
|
for (std::size_t i = 0; i < hardcoded_size; ++i) {
|
|
|
|
values.push_back(GetRegister(instr.gpr0.Value() + i));
|
|
|
|
}
|
|
|
|
|
2019-09-18 00:07:01 -04:00
|
|
|
const auto type{instr.suldst.image_type};
|
|
|
|
auto& image{instr.suldst.is_immediate ? GetImage(instr.image, type)
|
|
|
|
: GetBindlessImage(instr.gpr39, type)};
|
2019-09-05 22:26:05 -04:00
|
|
|
image.MarkWrite();
|
|
|
|
|
2019-09-18 00:07:01 -04:00
|
|
|
MetaImage meta{image, std::move(values)};
|
|
|
|
bb.push_back(Operation(OperationCode::ImageStore, meta, GetCoordinates(type)));
|
2019-07-17 20:03:53 -04:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
case OpCode::Id::SUATOM: {
|
|
|
|
UNIMPLEMENTED_IF(instr.suatom_d.is_ba != 0);
|
|
|
|
|
|
|
|
const OperationCode operation_code = [instr] {
|
2019-09-18 00:50:40 -04:00
|
|
|
switch (instr.suatom_d.operation_type) {
|
|
|
|
case Tegra::Shader::ImageAtomicOperationType::S32:
|
|
|
|
case Tegra::Shader::ImageAtomicOperationType::U32:
|
|
|
|
switch (instr.suatom_d.operation) {
|
|
|
|
case Tegra::Shader::ImageAtomicOperation::Add:
|
|
|
|
return OperationCode::AtomicImageAdd;
|
|
|
|
case Tegra::Shader::ImageAtomicOperation::And:
|
|
|
|
return OperationCode::AtomicImageAnd;
|
|
|
|
case Tegra::Shader::ImageAtomicOperation::Or:
|
|
|
|
return OperationCode::AtomicImageOr;
|
|
|
|
case Tegra::Shader::ImageAtomicOperation::Xor:
|
|
|
|
return OperationCode::AtomicImageXor;
|
|
|
|
case Tegra::Shader::ImageAtomicOperation::Exch:
|
|
|
|
return OperationCode::AtomicImageExchange;
|
|
|
|
}
|
2019-07-17 20:03:53 -04:00
|
|
|
default:
|
2019-09-18 00:50:40 -04:00
|
|
|
break;
|
2019-07-17 20:03:53 -04:00
|
|
|
}
|
2019-09-18 00:50:40 -04:00
|
|
|
UNIMPLEMENTED_MSG("Unimplemented operation={} type={}",
|
|
|
|
static_cast<u64>(instr.suatom_d.operation.Value()),
|
|
|
|
static_cast<u64>(instr.suatom_d.operation_type.Value()));
|
|
|
|
return OperationCode::AtomicImageAdd;
|
2019-07-17 20:03:53 -04:00
|
|
|
}();
|
|
|
|
|
2019-09-18 00:07:01 -04:00
|
|
|
Node value = GetRegister(instr.gpr0);
|
|
|
|
|
|
|
|
const auto type = instr.suatom_d.image_type;
|
2019-09-18 00:50:40 -04:00
|
|
|
auto& image = GetImage(instr.image, type);
|
|
|
|
image.MarkAtomic();
|
2019-09-18 00:07:01 -04:00
|
|
|
|
2019-07-17 20:03:53 -04:00
|
|
|
MetaImage meta{image, {std::move(value)}};
|
2019-09-18 00:07:01 -04:00
|
|
|
SetRegister(bb, instr.gpr0, Operation(operation_code, meta, GetCoordinates(type)));
|
2019-04-27 01:07:18 -04:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
default:
|
2019-09-05 22:26:05 -04:00
|
|
|
UNIMPLEMENTED_MSG("Unhandled image instruction: {}", opcode->get().GetName());
|
2019-04-27 01:07:18 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
return pc;
|
|
|
|
}
|
|
|
|
|
2019-09-18 00:50:40 -04:00
|
|
|
Image& ShaderIR::GetImage(Tegra::Shader::Image image, Tegra::Shader::ImageType type) {
|
2019-10-28 01:31:05 -04:00
|
|
|
const auto offset = static_cast<u32>(image.index.Value());
|
|
|
|
|
|
|
|
const auto it =
|
|
|
|
std::find_if(std::begin(used_images), std::end(used_images),
|
|
|
|
[offset](const Image& entry) { return entry.GetOffset() == offset; });
|
|
|
|
if (it != std::end(used_images)) {
|
|
|
|
ASSERT(!it->IsBindless() && it->GetType() == it->GetType());
|
|
|
|
return *it;
|
2019-04-27 01:07:18 -04:00
|
|
|
}
|
|
|
|
|
2019-10-28 01:31:05 -04:00
|
|
|
const auto next_index = static_cast<u32>(used_images.size());
|
|
|
|
return used_images.emplace_back(next_index, offset, type);
|
2019-04-27 01:07:18 -04:00
|
|
|
}
|
|
|
|
|
2019-09-18 00:50:40 -04:00
|
|
|
Image& ShaderIR::GetBindlessImage(Tegra::Shader::Register reg, Tegra::Shader::ImageType type) {
|
2019-10-28 01:31:05 -04:00
|
|
|
const Node image_register = GetRegister(reg);
|
|
|
|
const auto [base_image, buffer, offset] =
|
|
|
|
TrackCbuf(image_register, global_code, static_cast<s64>(global_code.size()));
|
|
|
|
|
|
|
|
const auto it =
|
|
|
|
std::find_if(std::begin(used_images), std::end(used_images),
|
|
|
|
[buffer = buffer, offset = offset](const Image& entry) {
|
|
|
|
return entry.GetBuffer() == buffer && entry.GetOffset() == offset;
|
|
|
|
});
|
|
|
|
if (it != std::end(used_images)) {
|
|
|
|
ASSERT(it->IsBindless() && it->GetType() == it->GetType());
|
|
|
|
return *it;
|
2019-07-17 20:03:53 -04:00
|
|
|
}
|
|
|
|
|
2019-10-28 01:31:05 -04:00
|
|
|
const auto next_index = static_cast<u32>(used_images.size());
|
|
|
|
return used_images.emplace_back(next_index, offset, buffer, type);
|
2019-07-17 20:03:53 -04:00
|
|
|
}
|
|
|
|
|
2019-04-27 01:07:18 -04:00
|
|
|
} // namespace VideoCommon::Shader
|