fix notNarrow VectorExtract, and add a tiny test to be sure that EmitSaturatingOp with notNarrow flag doesn't send errors
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3 changed files with 19 additions and 3 deletions
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@ -884,7 +884,9 @@ namespace ChocolArm64.Instruction
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Elems = !Scalar ? 8 >> Op.Size : 1;
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int Bytes = Op.GetBitsCount() >> 3;
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int Elems = !Scalar ? (Narrow ? 8 : Bytes) >> Op.Size : 1;
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int ESize = 8 << Op.Size;
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@ -912,11 +914,11 @@ namespace ChocolArm64.Instruction
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AILLabel LblLe = new AILLabel();
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AILLabel LblGeEnd = new AILLabel();
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size + 1, SignedSrc);
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EmitVectorExtract(Context, Op.Rn, Index, Narrow ? Op.Size + 1 : Op.Size, SignedSrc);
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if (Binary)
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{
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EmitVectorExtract(Context, ((AOpCodeSimdReg)Op).Rm, Index, Op.Size + 1, SignedSrc);
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EmitVectorExtract(Context, ((AOpCodeSimdReg)Op).Rm, Index, Narrow ? Op.Size + 1 : Op.Size, SignedSrc);
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}
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Emit();
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@ -1126,6 +1126,19 @@ namespace Ryujinx.Tests.Cpu
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});
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}
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[TestCase(0x00000001u, 0x7FFFFFFFu, 0x7FFFFFFFu, true)]
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public void Sqadd_S(uint A, uint B, uint Result, bool Fpsr)
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{
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Vector128<float> V1 = MakeVectorE0(A);
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Vector128<float> V2 = MakeVectorE0(B);
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AThreadState ThreadState = SingleOpcode(0x5EA20C20, V1: V1, V2: V2);
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Assert.Multiple(() =>
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{
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Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
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Assert.AreEqual(((ThreadState.Fpsr >> 27) & 1) == 1, Fpsr);
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});
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}
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[Test, Description("SQXTN <Vb><d>, <Va><n>")]
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public void Sqxtn_S_HB_SH_DS([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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@ -9,6 +9,7 @@ namespace Ryujinx.Tests.Cpu
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{
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public class CpuTestSimdArithmetic : CpuTest
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{
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[TestCase(0x1E224820u, 0x0000000000000000ul, 0x0000000080000000ul, 0x0000000000000000ul)]
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[TestCase(0x1E224820u, 0x0000000080000000ul, 0x0000000000000000ul, 0x0000000000000000ul)]
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[TestCase(0x1E224820u, 0x0000000080000000ul, 0x0000000080000000ul, 0x0000000080000000ul)]
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