2019-03-14 23:37:54 -04:00
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using Ryujinx.Common.Logging;
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2020-05-03 18:54:50 -04:00
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using Ryujinx.Cpu;
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2018-12-18 00:33:36 -05:00
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using Ryujinx.HLE.HOS.Kernel.Common;
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using Ryujinx.HLE.HOS.Kernel.Process;
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2018-09-18 19:36:43 -04:00
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using System;
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2018-05-14 02:01:10 -04:00
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using System.Collections.Generic;
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2018-09-18 19:36:43 -04:00
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using System.Linq;
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2019-03-14 23:37:54 -04:00
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using System.Text;
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Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 14:56:22 -04:00
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using System.Threading;
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2018-09-18 19:36:43 -04:00
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2018-12-18 00:33:36 -05:00
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namespace Ryujinx.HLE.HOS.Kernel.Threading
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2018-02-04 18:08:20 -05:00
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{
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2018-09-18 19:36:43 -04:00
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class KThread : KSynchronizationObject, IKFutureSchedulerObject
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2018-02-04 18:08:20 -05:00
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{
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2020-07-17 00:22:13 -04:00
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public const int MaxWaitSyncObjects = 64;
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Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 14:56:22 -04:00
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private int _hostThreadRunning;
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public Thread HostThread { get; private set; }
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2019-10-31 14:09:03 -04:00
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public ARMeilleure.State.ExecutionContext Context { get; private set; }
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2018-02-04 18:08:20 -05:00
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2018-09-18 19:36:43 -04:00
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public long AffinityMask { get; set; }
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2018-05-12 23:22:42 -04:00
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2018-11-28 17:18:09 -05:00
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public long ThreadUid { get; private set; }
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2018-04-21 15:07:16 -04:00
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2018-11-28 17:18:09 -05:00
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public long TotalTimeRunning { get; set; }
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public KSynchronizationObject SignaledObj { get; set; }
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2018-05-15 21:36:08 -04:00
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2018-12-18 00:33:36 -05:00
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public ulong CondVarAddress { get; set; }
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2018-05-12 23:22:42 -04:00
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2018-12-06 06:16:24 -05:00
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private ulong _entrypoint;
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2020-12-01 18:23:43 -05:00
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private ThreadStart _customThreadStart;
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2018-11-28 17:18:09 -05:00
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2018-12-18 00:33:36 -05:00
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public ulong MutexAddress { get; set; }
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2018-11-28 17:18:09 -05:00
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public KProcess Owner { get; private set; }
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2018-04-21 15:07:16 -04:00
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2018-12-06 06:16:24 -05:00
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private ulong _tlsAddress;
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2018-11-28 17:18:09 -05:00
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2019-01-18 17:26:39 -05:00
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public ulong TlsAddress => _tlsAddress;
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public ulong TlsDramAddress { get; private set; }
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2020-07-17 00:22:13 -04:00
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public KSynchronizationObject[] WaitSyncObjects { get; }
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public int[] WaitSyncHandles { get; }
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2018-11-28 17:18:09 -05:00
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public long LastScheduledTime { get; set; }
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2018-04-21 15:07:16 -04:00
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2018-12-04 19:52:39 -05:00
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public LinkedListNode<KThread>[] SiblingsPerCore { get; private set; }
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2018-04-21 15:07:16 -04:00
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2020-12-01 18:23:43 -05:00
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public LinkedList<KThread> Withholder { get; set; }
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2018-11-28 17:18:09 -05:00
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public LinkedListNode<KThread> WithholderNode { get; set; }
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public LinkedListNode<KThread> ProcessListNode { get; set; }
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2018-04-18 22:52:23 -04:00
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2020-12-01 18:23:43 -05:00
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private LinkedList<KThread> _mutexWaiters;
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2018-12-06 06:16:24 -05:00
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private LinkedListNode<KThread> _mutexWaiterNode;
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2018-02-13 21:43:08 -05:00
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2018-09-18 19:36:43 -04:00
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public KThread MutexOwner { get; private set; }
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2018-06-26 00:09:32 -04:00
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2018-09-18 19:36:43 -04:00
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public int ThreadHandleForUserMutex { get; set; }
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2018-12-06 06:16:24 -05:00
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private ThreadSchedState _forcePauseFlags;
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2018-09-18 19:36:43 -04:00
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2018-12-18 00:33:36 -05:00
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public KernelResult ObjSyncResult { get; set; }
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2018-09-18 19:36:43 -04:00
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public int DynamicPriority { get; set; }
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2020-12-01 18:23:43 -05:00
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public int CurrentCore { get; set; }
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public int BasePriority { get; set; }
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public int PreferredCore { get; set; }
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2018-09-18 19:36:43 -04:00
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2018-12-06 06:16:24 -05:00
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private long _affinityMaskOverride;
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2020-12-01 18:23:43 -05:00
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private int _preferredCoreOverride;
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2020-04-20 17:59:59 -04:00
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#pragma warning disable CS0649
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2020-12-01 18:23:43 -05:00
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private int _affinityOverrideCount;
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2020-04-20 17:59:59 -04:00
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#pragma warning restore CS0649
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2018-09-18 19:36:43 -04:00
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public ThreadSchedState SchedFlags { get; private set; }
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2019-12-25 20:50:17 -05:00
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private int _shallBeTerminated;
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2020-12-01 18:23:43 -05:00
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public bool ShallBeTerminated
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{
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get => _shallBeTerminated != 0;
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set => _shallBeTerminated = value ? 1 : 0;
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}
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2018-09-18 19:36:43 -04:00
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public bool SyncCancelled { get; set; }
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2020-12-01 18:23:43 -05:00
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public bool WaitingSync { get; set; }
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2018-09-18 19:36:43 -04:00
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2018-12-06 06:16:24 -05:00
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private bool _hasExited;
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2019-01-18 17:26:39 -05:00
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private bool _hasBeenInitialized;
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private bool _hasBeenReleased;
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2018-09-18 19:36:43 -04:00
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public bool WaitingInArbitration { get; set; }
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2018-12-06 06:16:24 -05:00
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private KScheduler _scheduler;
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2018-09-18 19:36:43 -04:00
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2018-12-06 06:16:24 -05:00
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private KSchedulingData _schedulingData;
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2018-09-18 19:36:43 -04:00
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public long LastPc { get; set; }
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2018-02-13 21:43:08 -05:00
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2020-05-03 23:41:29 -04:00
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public KThread(KernelContext context) : base(context)
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2018-02-04 18:08:20 -05:00
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{
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2020-12-01 18:23:43 -05:00
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_scheduler = KernelContext.Scheduler;
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2020-05-03 23:41:29 -04:00
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_schedulingData = KernelContext.Scheduler.SchedulingData;
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2018-05-12 23:22:42 -04:00
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2020-07-17 00:22:13 -04:00
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WaitSyncObjects = new KSynchronizationObject[MaxWaitSyncObjects];
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WaitSyncHandles = new int[MaxWaitSyncObjects];
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2018-09-18 19:36:43 -04:00
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SiblingsPerCore = new LinkedListNode<KThread>[KScheduler.CpuCoresCount];
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2018-05-14 02:01:10 -04:00
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2018-12-06 06:16:24 -05:00
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_mutexWaiters = new LinkedList<KThread>();
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2018-11-28 17:18:09 -05:00
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}
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public KernelResult Initialize(
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2020-12-01 18:23:43 -05:00
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ulong entrypoint,
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ulong argsPtr,
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ulong stackTop,
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int priority,
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int defaultCpuCore,
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KProcess owner,
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ThreadType type,
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ThreadStart customThreadStart = null)
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2018-11-28 17:18:09 -05:00
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{
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2018-12-06 06:16:24 -05:00
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if ((uint)type > 3)
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2018-11-28 17:18:09 -05:00
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{
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2018-12-06 06:16:24 -05:00
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throw new ArgumentException($"Invalid thread type \"{type}\".");
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2018-11-28 17:18:09 -05:00
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}
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2018-04-21 15:07:16 -04:00
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2018-12-06 06:16:24 -05:00
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PreferredCore = defaultCpuCore;
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2018-09-18 19:36:43 -04:00
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2018-12-06 06:16:24 -05:00
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AffinityMask |= 1L << defaultCpuCore;
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2018-11-28 17:18:09 -05:00
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2018-12-06 06:16:24 -05:00
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SchedFlags = type == ThreadType.Dummy
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2018-11-28 17:18:09 -05:00
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? ThreadSchedState.Running
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: ThreadSchedState.None;
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2018-09-18 19:36:43 -04:00
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CurrentCore = PreferredCore;
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2018-11-28 17:18:09 -05:00
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2018-12-06 06:16:24 -05:00
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DynamicPriority = priority;
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2020-12-01 18:23:43 -05:00
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BasePriority = priority;
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2018-11-28 17:18:09 -05:00
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2018-12-18 00:33:36 -05:00
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ObjSyncResult = KernelResult.ThreadNotStarted;
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2018-11-28 17:18:09 -05:00
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2018-12-06 06:16:24 -05:00
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_entrypoint = entrypoint;
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2020-12-01 18:23:43 -05:00
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_customThreadStart = customThreadStart;
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2018-11-28 17:18:09 -05:00
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2018-12-06 06:16:24 -05:00
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if (type == ThreadType.User)
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2018-11-28 17:18:09 -05:00
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{
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2018-12-06 06:16:24 -05:00
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if (owner.AllocateThreadLocalStorage(out _tlsAddress) != KernelResult.Success)
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2018-11-28 17:18:09 -05:00
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{
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return KernelResult.OutOfMemory;
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}
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2019-01-18 17:26:39 -05:00
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TlsDramAddress = owner.MemoryManager.GetDramAddressFromVa(_tlsAddress);
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2018-12-06 06:16:24 -05:00
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MemoryHelper.FillWithZeros(owner.CpuMemory, (long)_tlsAddress, KTlsPageInfo.TlsEntrySize);
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2018-11-28 17:18:09 -05:00
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}
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2018-12-06 06:16:24 -05:00
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bool is64Bits;
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2018-11-28 17:18:09 -05:00
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2018-12-06 06:16:24 -05:00
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if (owner != null)
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2018-11-28 17:18:09 -05:00
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{
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2018-12-06 06:16:24 -05:00
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Owner = owner;
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2018-11-28 17:18:09 -05:00
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2019-01-18 17:26:39 -05:00
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owner.IncrementReferenceCount();
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2018-12-06 06:16:24 -05:00
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owner.IncrementThreadCount();
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2018-11-28 17:18:09 -05:00
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2020-12-01 18:23:43 -05:00
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is64Bits = owner.Flags.HasFlag(ProcessCreationFlags.Is64Bit);
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2018-11-28 17:18:09 -05:00
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}
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else
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{
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2018-12-06 06:16:24 -05:00
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is64Bits = true;
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2018-11-28 17:18:09 -05:00
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}
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2020-12-01 18:23:43 -05:00
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HostThread = new Thread(ThreadStart);
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2018-11-28 17:18:09 -05:00
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2020-05-03 18:54:50 -04:00
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Context = CpuContext.CreateExecutionContext();
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Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)
* Rename some opcode classes and flag masks for consistency
* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations
* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC
* Re-align arm32 instructions on the opcode table
2019-01-29 11:06:11 -05:00
|
|
|
|
2020-12-01 18:23:43 -05:00
|
|
|
bool isAarch32 = !Owner.Flags.HasFlag(ProcessCreationFlags.Is64Bit);
|
2019-01-24 20:59:53 -05:00
|
|
|
|
2019-11-14 09:28:13 -05:00
|
|
|
Context.IsAarch32 = isAarch32;
|
|
|
|
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 14:56:22 -04:00
|
|
|
Context.SetX(0, argsPtr);
|
Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)
* Rename some opcode classes and flag masks for consistency
* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations
* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC
* Re-align arm32 instructions on the opcode table
2019-01-29 11:06:11 -05:00
|
|
|
|
|
|
|
if (isAarch32)
|
|
|
|
{
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 14:56:22 -04:00
|
|
|
Context.SetX(13, (uint)stackTop);
|
Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)
* Rename some opcode classes and flag masks for consistency
* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations
* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC
* Re-align arm32 instructions on the opcode table
2019-01-29 11:06:11 -05:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 14:56:22 -04:00
|
|
|
Context.SetX(31, stackTop);
|
Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)
* Rename some opcode classes and flag masks for consistency
* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations
* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC
* Re-align arm32 instructions on the opcode table
2019-01-29 11:06:11 -05:00
|
|
|
}
|
2018-11-28 17:18:09 -05:00
|
|
|
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 14:56:22 -04:00
|
|
|
Context.CntfrqEl0 = 19200000;
|
2020-12-01 18:23:43 -05:00
|
|
|
Context.Tpidr = (long)_tlsAddress;
|
2018-11-28 17:18:09 -05:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
owner.SubscribeThreadEventHandlers(Context);
|
2018-11-28 17:18:09 -05:00
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
ThreadUid = KernelContext.NewThreadUid();
|
2018-11-28 17:18:09 -05:00
|
|
|
|
2020-01-12 19:21:54 -05:00
|
|
|
HostThread.Name = $"HLE.HostThread.{ThreadUid}";
|
2019-12-25 20:50:17 -05:00
|
|
|
|
2019-01-18 17:26:39 -05:00
|
|
|
_hasBeenInitialized = true;
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (owner != null)
|
2018-11-28 17:18:09 -05:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
owner.AddThread(this);
|
2018-11-28 17:18:09 -05:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (owner.IsPaused)
|
2018-11-28 17:18:09 -05:00
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-11-28 17:18:09 -05:00
|
|
|
|
|
|
|
if (ShallBeTerminated || SchedFlags == ThreadSchedState.TerminationPending)
|
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-11-28 17:18:09 -05:00
|
|
|
|
|
|
|
return KernelResult.Success;
|
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
_forcePauseFlags |= ThreadSchedState.ProcessPauseFlag;
|
2018-11-28 17:18:09 -05:00
|
|
|
|
|
|
|
CombineForcePauseFlags();
|
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-11-28 17:18:09 -05:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return KernelResult.Success;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2018-11-28 17:18:09 -05:00
|
|
|
public KernelResult Start()
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
if (!KernelContext.KernelInitialized)
|
2018-11-28 17:18:09 -05:00
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-11-28 17:18:09 -05:00
|
|
|
|
|
|
|
if (!ShallBeTerminated && SchedFlags != ThreadSchedState.TerminationPending)
|
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
_forcePauseFlags |= ThreadSchedState.KernelInitPauseFlag;
|
2018-11-28 17:18:09 -05:00
|
|
|
|
|
|
|
CombineForcePauseFlags();
|
|
|
|
}
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-11-28 17:18:09 -05:00
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
KernelResult result = KernelResult.ThreadTerminating;
|
2018-11-28 17:18:09 -05:00
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
if (!ShallBeTerminated)
|
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KThread currentThread = KernelContext.Scheduler.GetCurrentThread();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2020-12-01 18:23:43 -05:00
|
|
|
while (SchedFlags != ThreadSchedState.TerminationPending &&
|
2018-12-06 06:16:24 -05:00
|
|
|
currentThread.SchedFlags != ThreadSchedState.TerminationPending &&
|
|
|
|
!currentThread.ShallBeTerminated)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-11-28 17:18:09 -05:00
|
|
|
if ((SchedFlags & ThreadSchedState.LowMask) != ThreadSchedState.None)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
result = KernelResult.InvalidState;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (currentThread._forcePauseFlags == ThreadSchedState.None)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
if (Owner != null && _forcePauseFlags != ThreadSchedState.None)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
|
|
|
CombineForcePauseFlags();
|
|
|
|
}
|
|
|
|
|
|
|
|
SetNewSchedFlags(ThreadSchedState.Running);
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
result = KernelResult.Success;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
currentThread.CombineForcePauseFlags();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (currentThread.ShallBeTerminated)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
return result;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
public void Exit()
|
|
|
|
{
|
2019-07-01 22:39:22 -04:00
|
|
|
// TODO: Debug event.
|
2019-01-18 17:26:39 -05:00
|
|
|
|
|
|
|
if (Owner != null)
|
|
|
|
{
|
|
|
|
Owner.ResourceLimit?.Release(LimitableResource.Thread, 0, 1);
|
|
|
|
|
|
|
|
_hasBeenReleased = true;
|
|
|
|
}
|
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
_forcePauseFlags &= ~ThreadSchedState.ForcePauseMask;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
ExitImpl();
|
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2019-01-18 17:26:39 -05:00
|
|
|
|
|
|
|
DecrementReferenceCount();
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2019-12-25 20:50:17 -05:00
|
|
|
public ThreadSchedState PrepareForTermination()
|
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2019-12-25 20:50:17 -05:00
|
|
|
|
|
|
|
ThreadSchedState result;
|
|
|
|
|
|
|
|
if (Interlocked.CompareExchange(ref _shallBeTerminated, 1, 0) == 0)
|
|
|
|
{
|
|
|
|
if ((SchedFlags & ThreadSchedState.LowMask) == ThreadSchedState.None)
|
|
|
|
{
|
|
|
|
SchedFlags = ThreadSchedState.TerminationPending;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (_forcePauseFlags != ThreadSchedState.None)
|
|
|
|
{
|
|
|
|
_forcePauseFlags &= ~ThreadSchedState.ThreadPauseFlag;
|
|
|
|
|
|
|
|
ThreadSchedState oldSchedFlags = SchedFlags;
|
|
|
|
|
|
|
|
SchedFlags &= ThreadSchedState.LowMask;
|
|
|
|
|
|
|
|
AdjustScheduling(oldSchedFlags);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (BasePriority >= 0x10)
|
|
|
|
{
|
|
|
|
SetPriority(0xF);
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((SchedFlags & ThreadSchedState.LowMask) == ThreadSchedState.Running)
|
|
|
|
{
|
|
|
|
// TODO: GIC distributor stuffs (sgir changes ect)
|
2020-09-22 00:50:40 -04:00
|
|
|
Context.RequestInterrupt();
|
2019-12-25 20:50:17 -05:00
|
|
|
}
|
|
|
|
|
2020-12-01 18:23:43 -05:00
|
|
|
SignaledObj = null;
|
2019-12-25 20:50:17 -05:00
|
|
|
ObjSyncResult = KernelResult.ThreadTerminating;
|
|
|
|
|
|
|
|
ReleaseAndResume();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
result = SchedFlags;
|
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2019-12-25 20:50:17 -05:00
|
|
|
|
|
|
|
return result & ThreadSchedState.LowMask;
|
|
|
|
}
|
|
|
|
|
|
|
|
public void Terminate()
|
|
|
|
{
|
|
|
|
ThreadSchedState state = PrepareForTermination();
|
|
|
|
|
|
|
|
if (state != ThreadSchedState.TerminationPending)
|
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.Synchronization.WaitFor(new KSynchronizationObject[] { this }, -1, out _);
|
2019-12-25 20:50:17 -05:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
public void HandlePostSyscall()
|
|
|
|
{
|
|
|
|
ThreadSchedState state;
|
|
|
|
|
|
|
|
do
|
|
|
|
{
|
|
|
|
if (ShallBeTerminated || SchedFlags == ThreadSchedState.TerminationPending)
|
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.Scheduler.ExitThread(this);
|
2019-12-25 20:50:17 -05:00
|
|
|
Exit();
|
|
|
|
|
|
|
|
// As the death of the thread is handled by the CPU emulator, we differ from the official kernel and return here.
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2019-12-25 20:50:17 -05:00
|
|
|
|
|
|
|
if (ShallBeTerminated || SchedFlags == ThreadSchedState.TerminationPending)
|
|
|
|
{
|
|
|
|
state = ThreadSchedState.TerminationPending;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (_forcePauseFlags != ThreadSchedState.None)
|
|
|
|
{
|
|
|
|
CombineForcePauseFlags();
|
|
|
|
}
|
|
|
|
|
|
|
|
state = ThreadSchedState.Running;
|
|
|
|
}
|
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2019-12-25 20:50:17 -05:00
|
|
|
} while (state == ThreadSchedState.TerminationPending);
|
|
|
|
}
|
|
|
|
|
2018-09-18 19:36:43 -04:00
|
|
|
private void ExitImpl()
|
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
SetNewSchedFlags(ThreadSchedState.TerminationPending);
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
_hasExited = true;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
Signal();
|
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2018-12-18 00:33:36 -05:00
|
|
|
public KernelResult Sleep(long timeout)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
if (ShallBeTerminated || SchedFlags == ThreadSchedState.TerminationPending)
|
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-18 00:33:36 -05:00
|
|
|
return KernelResult.ThreadTerminating;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
SetNewSchedFlags(ThreadSchedState.Paused);
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (timeout > 0)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.TimeManager.ScheduleFutureInvocation(this, timeout);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (timeout > 0)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.TimeManager.UnscheduleFutureInvocation(this);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
public void Yield()
|
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
if (SchedFlags != ThreadSchedState.Running)
|
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.Scheduler.ContextSwitch();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (DynamicPriority < KScheduler.PrioritiesCount)
|
|
|
|
{
|
2019-07-01 22:39:22 -04:00
|
|
|
// Move current thread to the end of the queue.
|
2018-12-06 06:16:24 -05:00
|
|
|
_schedulingData.Reschedule(DynamicPriority, CurrentCore, this);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
_scheduler.ThreadReselectionRequested = true;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.Scheduler.ContextSwitch();
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
public void YieldWithLoadBalancing()
|
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
if (SchedFlags != ThreadSchedState.Running)
|
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.Scheduler.ContextSwitch();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
int prio = DynamicPriority;
|
|
|
|
int core = CurrentCore;
|
2018-11-28 17:18:09 -05:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
KThread nextThreadOnCurrentQueue = null;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
if (DynamicPriority < KScheduler.PrioritiesCount)
|
|
|
|
{
|
2019-07-01 22:39:22 -04:00
|
|
|
// Move current thread to the end of the queue.
|
2018-12-06 06:16:24 -05:00
|
|
|
_schedulingData.Reschedule(prio, core, this);
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
Func<KThread, bool> predicate = x => x.DynamicPriority == prio;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
nextThreadOnCurrentQueue = _schedulingData.ScheduledThreads(core).FirstOrDefault(predicate);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
IEnumerable<KThread> SuitableCandidates()
|
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
foreach (KThread thread in _schedulingData.SuggestedThreads(core))
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
int srcCore = thread.CurrentCore;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (srcCore >= 0)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
KThread selectedSrcCore = _scheduler.CoreContexts[srcCore].SelectedThread;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (selectedSrcCore == thread || ((selectedSrcCore?.DynamicPriority ?? 2) < 2))
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-07-01 22:39:22 -04:00
|
|
|
// If the candidate was scheduled after the current thread, then it's not worth it,
|
|
|
|
// unless the priority is higher than the current one.
|
2018-12-06 06:16:24 -05:00
|
|
|
if (nextThreadOnCurrentQueue.LastScheduledTime >= thread.LastScheduledTime ||
|
2020-12-01 18:23:43 -05:00
|
|
|
nextThreadOnCurrentQueue.DynamicPriority < thread.DynamicPriority)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
yield return thread;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
KThread dst = SuitableCandidates().FirstOrDefault(x => x.DynamicPriority <= prio);
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (dst != null)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
_schedulingData.TransferToCore(dst.DynamicPriority, core, dst);
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
_scheduler.ThreadReselectionRequested = true;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (this != nextThreadOnCurrentQueue)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
_scheduler.ThreadReselectionRequested = true;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.Scheduler.ContextSwitch();
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
public void YieldAndWaitForLoadBalancing()
|
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
if (SchedFlags != ThreadSchedState.Running)
|
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.Scheduler.ContextSwitch();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
int core = CurrentCore;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
_schedulingData.TransferToCore(DynamicPriority, -1, this);
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
KThread selectedThread = null;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (!_schedulingData.ScheduledThreads(core).Any())
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
foreach (KThread thread in _schedulingData.SuggestedThreads(core))
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
if (thread.CurrentCore < 0)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
KThread firstCandidate = _schedulingData.ScheduledThreads(thread.CurrentCore).FirstOrDefault();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (firstCandidate == thread)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (firstCandidate == null || firstCandidate.DynamicPriority >= 2)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
_schedulingData.TransferToCore(thread.DynamicPriority, core, thread);
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
selectedThread = thread;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (selectedThread != this)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
_scheduler.ThreadReselectionRequested = true;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.Scheduler.ContextSwitch();
|
2018-04-21 15:07:16 -04:00
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
public void SetPriority(int priority)
|
2018-04-21 15:07:16 -04:00
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-04-21 15:07:16 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
BasePriority = priority;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
UpdatePriorityInheritance();
|
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-04-21 15:07:16 -04:00
|
|
|
}
|
|
|
|
|
2018-12-18 00:33:36 -05:00
|
|
|
public KernelResult SetActivity(bool pause)
|
2018-04-21 15:07:16 -04:00
|
|
|
{
|
2018-12-18 00:33:36 -05:00
|
|
|
KernelResult result = KernelResult.Success;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
ThreadSchedState lowNibble = SchedFlags & ThreadSchedState.LowMask;
|
2018-04-21 15:07:16 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (lowNibble != ThreadSchedState.Paused && lowNibble != ThreadSchedState.Running)
|
2018-04-21 15:07:16 -04:00
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-06-21 22:05:42 -04:00
|
|
|
|
2018-12-18 00:33:36 -05:00
|
|
|
return KernelResult.InvalidState;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-06-21 22:05:42 -04:00
|
|
|
|
2018-09-18 19:36:43 -04:00
|
|
|
if (!ShallBeTerminated && SchedFlags != ThreadSchedState.TerminationPending)
|
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
if (pause)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2019-07-01 22:39:22 -04:00
|
|
|
// Pause, the force pause flag should be clear (thread is NOT paused).
|
2018-12-06 06:16:24 -05:00
|
|
|
if ((_forcePauseFlags & ThreadSchedState.ThreadPauseFlag) == 0)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
_forcePauseFlags |= ThreadSchedState.ThreadPauseFlag;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
CombineForcePauseFlags();
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2018-12-18 00:33:36 -05:00
|
|
|
result = KernelResult.InvalidState;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
2018-04-21 15:07:16 -04:00
|
|
|
{
|
2019-07-01 22:39:22 -04:00
|
|
|
// Unpause, the force pause flag should be set (thread is paused).
|
2018-12-06 06:16:24 -05:00
|
|
|
if ((_forcePauseFlags & ThreadSchedState.ThreadPauseFlag) != 0)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
ThreadSchedState oldForcePauseFlags = _forcePauseFlags;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
_forcePauseFlags &= ~ThreadSchedState.ThreadPauseFlag;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if ((oldForcePauseFlags & ~ThreadSchedState.ThreadPauseFlag) == ThreadSchedState.None)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
ThreadSchedState oldSchedFlags = SchedFlags;
|
2018-06-21 22:05:42 -04:00
|
|
|
|
2018-11-28 17:18:09 -05:00
|
|
|
SchedFlags &= ThreadSchedState.LowMask;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
AdjustScheduling(oldSchedFlags);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
2018-05-12 23:22:42 -04:00
|
|
|
{
|
2018-12-18 00:33:36 -05:00
|
|
|
result = KernelResult.InvalidState;
|
2018-05-12 23:22:42 -04:00
|
|
|
}
|
|
|
|
}
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
return result;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
public void CancelSynchronization()
|
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-11-28 17:18:09 -05:00
|
|
|
if ((SchedFlags & ThreadSchedState.LowMask) != ThreadSchedState.Paused || !WaitingSync)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
|
|
|
SyncCancelled = true;
|
|
|
|
}
|
2018-11-28 17:18:09 -05:00
|
|
|
else if (Withholder != null)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-11-28 17:18:09 -05:00
|
|
|
Withholder.Remove(WithholderNode);
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
SetNewSchedFlags(ThreadSchedState.Running);
|
2018-04-21 15:07:16 -04:00
|
|
|
|
2018-11-28 17:18:09 -05:00
|
|
|
Withholder = null;
|
2018-06-21 22:05:42 -04:00
|
|
|
|
2018-09-18 19:36:43 -04:00
|
|
|
SyncCancelled = true;
|
2018-06-21 22:05:42 -04:00
|
|
|
}
|
2018-09-18 19:36:43 -04:00
|
|
|
else
|
|
|
|
{
|
2020-12-01 18:23:43 -05:00
|
|
|
SignaledObj = null;
|
2018-12-18 00:33:36 -05:00
|
|
|
ObjSyncResult = KernelResult.Cancelled;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
SetNewSchedFlags(ThreadSchedState.Running);
|
|
|
|
|
|
|
|
SyncCancelled = false;
|
|
|
|
}
|
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
public KernelResult SetCoreAndAffinityMask(int newCore, long newAffinityMask)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
bool useOverride = _affinityOverrideCount != 0;
|
2018-05-12 23:22:42 -04:00
|
|
|
|
2019-07-01 22:39:22 -04:00
|
|
|
// The value -3 is "do not change the preferred core".
|
2018-12-06 06:16:24 -05:00
|
|
|
if (newCore == -3)
|
2018-06-21 22:05:42 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
newCore = useOverride ? _preferredCoreOverride : PreferredCore;
|
2018-05-12 23:22:42 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if ((newAffinityMask & (1 << newCore)) == 0)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-11-28 17:18:09 -05:00
|
|
|
return KernelResult.InvalidCombination;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
2018-04-21 15:07:16 -04:00
|
|
|
}
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (useOverride)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
_preferredCoreOverride = newCore;
|
2020-12-01 18:23:43 -05:00
|
|
|
_affinityMaskOverride = newAffinityMask;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
long oldAffinityMask = AffinityMask;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
PreferredCore = newCore;
|
2020-12-01 18:23:43 -05:00
|
|
|
AffinityMask = newAffinityMask;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (oldAffinityMask != newAffinityMask)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
int oldCore = CurrentCore;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
if (CurrentCore >= 0 && ((AffinityMask >> CurrentCore) & 1) == 0)
|
|
|
|
{
|
|
|
|
if (PreferredCore < 0)
|
|
|
|
{
|
|
|
|
CurrentCore = HighestSetCore(AffinityMask);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
CurrentCore = PreferredCore;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
AdjustSchedulingForNewAffinity(oldAffinityMask, oldCore);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-11-28 17:18:09 -05:00
|
|
|
return KernelResult.Success;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
private static int HighestSetCore(long mask)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
for (int core = KScheduler.CpuCoresCount - 1; core >= 0; core--)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
if (((mask >> core) & 1) != 0)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
return core;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
private void CombineForcePauseFlags()
|
|
|
|
{
|
2020-12-01 18:23:43 -05:00
|
|
|
ThreadSchedState oldFlags = SchedFlags;
|
2018-12-06 06:16:24 -05:00
|
|
|
ThreadSchedState lowNibble = SchedFlags & ThreadSchedState.LowMask;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
SchedFlags = lowNibble | _forcePauseFlags;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
AdjustScheduling(oldFlags);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
private void SetNewSchedFlags(ThreadSchedState newFlags)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
ThreadSchedState oldFlags = SchedFlags;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
SchedFlags = (oldFlags & ThreadSchedState.HighMask) | newFlags;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if ((oldFlags & ThreadSchedState.LowMask) != newFlags)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
AdjustScheduling(oldFlags);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
public void ReleaseAndResume()
|
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-11-28 17:18:09 -05:00
|
|
|
if ((SchedFlags & ThreadSchedState.LowMask) == ThreadSchedState.Paused)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-11-28 17:18:09 -05:00
|
|
|
if (Withholder != null)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-11-28 17:18:09 -05:00
|
|
|
Withholder.Remove(WithholderNode);
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
SetNewSchedFlags(ThreadSchedState.Running);
|
|
|
|
|
2018-11-28 17:18:09 -05:00
|
|
|
Withholder = null;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
SetNewSchedFlags(ThreadSchedState.Running);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
public void Reschedule(ThreadSchedState newFlags)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Enter();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
ThreadSchedState oldFlags = SchedFlags;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
SchedFlags = (oldFlags & ThreadSchedState.HighMask) |
|
|
|
|
(newFlags & ThreadSchedState.LowMask);
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
AdjustScheduling(oldFlags);
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
public void AddMutexWaiter(KThread requester)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
AddToMutexWaitersList(requester);
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
requester.MutexOwner = this;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
UpdatePriorityInheritance();
|
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
public void RemoveMutexWaiter(KThread thread)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
if (thread._mutexWaiterNode?.List != null)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
_mutexWaiters.Remove(thread._mutexWaiterNode);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
thread.MutexOwner = null;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
UpdatePriorityInheritance();
|
|
|
|
}
|
|
|
|
|
2018-12-18 00:33:36 -05:00
|
|
|
public KThread RelinquishMutex(ulong mutexAddress, out int count)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
count = 0;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (_mutexWaiters.First == null)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
|
|
|
return null;
|
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
KThread newMutexOwner = null;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
LinkedListNode<KThread> currentNode = _mutexWaiters.First;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
do
|
|
|
|
{
|
2019-07-01 22:39:22 -04:00
|
|
|
// Skip all threads that are not waiting for this mutex.
|
2018-12-06 06:16:24 -05:00
|
|
|
while (currentNode != null && currentNode.Value.MutexAddress != mutexAddress)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
currentNode = currentNode.Next;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (currentNode == null)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
LinkedListNode<KThread> nextNode = currentNode.Next;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
_mutexWaiters.Remove(currentNode);
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
currentNode.Value.MutexOwner = newMutexOwner;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (newMutexOwner != null)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2019-07-01 22:39:22 -04:00
|
|
|
// New owner was already selected, re-insert on new owner list.
|
2018-12-06 06:16:24 -05:00
|
|
|
newMutexOwner.AddToMutexWaitersList(currentNode.Value);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2019-07-01 22:39:22 -04:00
|
|
|
// New owner not selected yet, use current thread.
|
2018-12-06 06:16:24 -05:00
|
|
|
newMutexOwner = currentNode.Value;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
count++;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
currentNode = nextNode;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
2018-12-06 06:16:24 -05:00
|
|
|
while (currentNode != null);
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (newMutexOwner != null)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
|
|
|
UpdatePriorityInheritance();
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
newMutexOwner.UpdatePriorityInheritance();
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
return newMutexOwner;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
private void UpdatePriorityInheritance()
|
|
|
|
{
|
2019-07-01 22:39:22 -04:00
|
|
|
// If any of the threads waiting for the mutex has
|
|
|
|
// higher priority than the current thread, then
|
|
|
|
// the current thread inherits that priority.
|
2018-12-06 06:16:24 -05:00
|
|
|
int highestPriority = BasePriority;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (_mutexWaiters.First != null)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
int waitingDynamicPriority = _mutexWaiters.First.Value.DynamicPriority;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (waitingDynamicPriority < highestPriority)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
highestPriority = waitingDynamicPriority;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (highestPriority != DynamicPriority)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
int oldPriority = DynamicPriority;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
DynamicPriority = highestPriority;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
AdjustSchedulingForNewPriority(oldPriority);
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
if (MutexOwner != null)
|
|
|
|
{
|
2019-07-01 22:39:22 -04:00
|
|
|
// Remove and re-insert to ensure proper sorting based on new priority.
|
2018-12-06 06:16:24 -05:00
|
|
|
MutexOwner._mutexWaiters.Remove(_mutexWaiterNode);
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
MutexOwner.AddToMutexWaitersList(this);
|
|
|
|
|
|
|
|
MutexOwner.UpdatePriorityInheritance();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
private void AddToMutexWaitersList(KThread thread)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
LinkedListNode<KThread> nextPrio = _mutexWaiters.First;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
int currentPriority = thread.DynamicPriority;
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
while (nextPrio != null && nextPrio.Value.DynamicPriority <= currentPriority)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
nextPrio = nextPrio.Next;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (nextPrio != null)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
thread._mutexWaiterNode = _mutexWaiters.AddBefore(nextPrio, thread);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
thread._mutexWaiterNode = _mutexWaiters.AddLast(thread);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
private void AdjustScheduling(ThreadSchedState oldFlags)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
if (oldFlags == SchedFlags)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
if (oldFlags == ThreadSchedState.Running)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2019-07-01 22:39:22 -04:00
|
|
|
// Was running, now it's stopped.
|
2018-09-18 19:36:43 -04:00
|
|
|
if (CurrentCore >= 0)
|
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
_schedulingData.Unschedule(DynamicPriority, CurrentCore, this);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
for (int core = 0; core < KScheduler.CpuCoresCount; core++)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
if (core != CurrentCore && ((AffinityMask >> core) & 1) != 0)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
_schedulingData.Unsuggest(DynamicPriority, core, this);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else if (SchedFlags == ThreadSchedState.Running)
|
|
|
|
{
|
2019-07-01 22:39:22 -04:00
|
|
|
// Was stopped, now it's running.
|
2018-09-18 19:36:43 -04:00
|
|
|
if (CurrentCore >= 0)
|
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
_schedulingData.Schedule(DynamicPriority, CurrentCore, this);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
for (int core = 0; core < KScheduler.CpuCoresCount; core++)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
if (core != CurrentCore && ((AffinityMask >> core) & 1) != 0)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
_schedulingData.Suggest(DynamicPriority, core, this);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
_scheduler.ThreadReselectionRequested = true;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
private void AdjustSchedulingForNewPriority(int oldPriority)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
|
|
|
if (SchedFlags != ThreadSchedState.Running)
|
|
|
|
{
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2019-07-01 22:39:22 -04:00
|
|
|
// Remove thread from the old priority queues.
|
2018-09-18 19:36:43 -04:00
|
|
|
if (CurrentCore >= 0)
|
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
_schedulingData.Unschedule(oldPriority, CurrentCore, this);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
for (int core = 0; core < KScheduler.CpuCoresCount; core++)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
if (core != CurrentCore && ((AffinityMask >> core) & 1) != 0)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
_schedulingData.Unsuggest(oldPriority, core, this);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-07-01 22:39:22 -04:00
|
|
|
// Add thread to the new priority queues.
|
2018-12-06 06:16:24 -05:00
|
|
|
KThread currentThread = _scheduler.GetCurrentThread();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
|
|
|
if (CurrentCore >= 0)
|
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
if (currentThread == this)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
_schedulingData.SchedulePrepend(DynamicPriority, CurrentCore, this);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
_schedulingData.Schedule(DynamicPriority, CurrentCore, this);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
for (int core = 0; core < KScheduler.CpuCoresCount; core++)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
if (core != CurrentCore && ((AffinityMask >> core) & 1) != 0)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
_schedulingData.Suggest(DynamicPriority, core, this);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
_scheduler.ThreadReselectionRequested = true;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
private void AdjustSchedulingForNewAffinity(long oldAffinityMask, int oldCore)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
|
|
|
if (SchedFlags != ThreadSchedState.Running || DynamicPriority >= KScheduler.PrioritiesCount)
|
|
|
|
{
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2019-07-01 22:39:22 -04:00
|
|
|
// Remove thread from the old priority queues.
|
2018-12-06 06:16:24 -05:00
|
|
|
for (int core = 0; core < KScheduler.CpuCoresCount; core++)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
if (((oldAffinityMask >> core) & 1) != 0)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
if (core == oldCore)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
_schedulingData.Unschedule(DynamicPriority, core, this);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
_schedulingData.Unsuggest(DynamicPriority, core, this);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-07-01 22:39:22 -04:00
|
|
|
// Add thread to the new priority queues.
|
2018-12-06 06:16:24 -05:00
|
|
|
for (int core = 0; core < KScheduler.CpuCoresCount; core++)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
if (((AffinityMask >> core) & 1) != 0)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
if (core == CurrentCore)
|
2018-09-18 19:36:43 -04:00
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
_schedulingData.Schedule(DynamicPriority, core, this);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2018-12-06 06:16:24 -05:00
|
|
|
_schedulingData.Suggest(DynamicPriority, core, this);
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
_scheduler.ThreadReselectionRequested = true;
|
2018-09-18 19:36:43 -04:00
|
|
|
}
|
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
public void SetEntryArguments(long argsPtr, int threadHandle)
|
2018-11-28 17:18:09 -05:00
|
|
|
{
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 14:56:22 -04:00
|
|
|
Context.SetX(0, (ulong)argsPtr);
|
|
|
|
Context.SetX(1, (ulong)threadHandle);
|
2018-11-28 17:18:09 -05:00
|
|
|
}
|
|
|
|
|
2018-09-18 19:36:43 -04:00
|
|
|
public void TimeUp()
|
|
|
|
{
|
2018-11-28 17:18:09 -05:00
|
|
|
ReleaseAndResume();
|
|
|
|
}
|
|
|
|
|
2019-03-14 23:37:54 -04:00
|
|
|
public string GetGuestStackTrace()
|
|
|
|
{
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 14:56:22 -04:00
|
|
|
return Owner.Debugger.GetGuestStackTrace(Context);
|
2019-03-14 23:37:54 -04:00
|
|
|
}
|
|
|
|
|
2018-11-28 17:18:09 -05:00
|
|
|
public void PrintGuestStackTrace()
|
|
|
|
{
|
2020-08-03 19:32:53 -04:00
|
|
|
Logger.Info?.Print(LogClass.Cpu, $"Guest stack trace:\n{GetGuestStackTrace()}\n");
|
2018-11-28 17:18:09 -05:00
|
|
|
}
|
|
|
|
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 14:56:22 -04:00
|
|
|
public void Execute()
|
|
|
|
{
|
|
|
|
if (Interlocked.CompareExchange(ref _hostThreadRunning, 1, 0) == 0)
|
|
|
|
{
|
|
|
|
HostThread.Start();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-12-01 18:23:43 -05:00
|
|
|
private void ThreadStart()
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 14:56:22 -04:00
|
|
|
{
|
2020-12-01 18:23:43 -05:00
|
|
|
KernelStatic.SetKernelContext(KernelContext);
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 14:56:22 -04:00
|
|
|
|
2020-12-01 18:23:43 -05:00
|
|
|
if (_customThreadStart != null)
|
|
|
|
{
|
|
|
|
_customThreadStart();
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
Owner.Context.Execute(Context, _entrypoint);
|
|
|
|
}
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 14:56:22 -04:00
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.Scheduler.ExitThread(this);
|
|
|
|
KernelContext.Scheduler.RemoveThread(this);
|
2020-12-01 18:23:43 -05:00
|
|
|
|
|
|
|
Context.Dispose();
|
2019-01-18 17:26:39 -05:00
|
|
|
}
|
2018-11-28 17:18:09 -05:00
|
|
|
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 14:56:22 -04:00
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public bool IsCurrentHostThread()
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{
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return Thread.CurrentThread == HostThread;
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}
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2019-01-18 17:26:39 -05:00
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public override bool IsSignaled()
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{
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return _hasExited;
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}
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2018-11-28 17:18:09 -05:00
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2019-01-18 17:26:39 -05:00
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protected override void Destroy()
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{
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if (_hasBeenInitialized)
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{
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FreeResources();
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bool released = Owner != null || _hasBeenReleased;
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if (Owner != null)
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{
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Owner.ResourceLimit?.Release(LimitableResource.Thread, 1, released ? 0 : 1);
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Owner.DecrementReferenceCount();
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}
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else
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{
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2020-05-03 23:41:29 -04:00
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KernelContext.ResourceLimit.Release(LimitableResource.Thread, 1, released ? 0 : 1);
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2019-01-18 17:26:39 -05:00
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}
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}
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2018-11-28 17:18:09 -05:00
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}
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2019-01-18 17:26:39 -05:00
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private void FreeResources()
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2018-11-28 17:18:09 -05:00
|
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{
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Owner?.RemoveThread(this);
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2018-12-06 06:16:24 -05:00
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if (_tlsAddress != 0 && Owner.FreeThreadLocalStorage(_tlsAddress) != KernelResult.Success)
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2018-11-28 17:18:09 -05:00
|
|
|
{
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|
|
throw new InvalidOperationException("Unexpected failure freeing thread local storage.");
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|
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}
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2020-05-03 23:41:29 -04:00
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KernelContext.CriticalSection.Enter();
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2018-11-28 17:18:09 -05:00
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|
2019-07-01 22:39:22 -04:00
|
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// Wake up all threads that may be waiting for a mutex being held by this thread.
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2018-12-06 06:16:24 -05:00
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|
|
foreach (KThread thread in _mutexWaiters)
|
2018-11-28 17:18:09 -05:00
|
|
|
{
|
2020-12-01 18:23:43 -05:00
|
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thread.MutexOwner = null;
|
2018-12-06 06:16:24 -05:00
|
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thread._preferredCoreOverride = 0;
|
2020-12-01 18:23:43 -05:00
|
|
|
thread.ObjSyncResult = KernelResult.InvalidState;
|
2018-11-28 17:18:09 -05:00
|
|
|
|
2018-12-06 06:16:24 -05:00
|
|
|
thread.ReleaseAndResume();
|
2018-11-28 17:18:09 -05:00
|
|
|
}
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2020-05-03 23:41:29 -04:00
|
|
|
KernelContext.CriticalSection.Leave();
|
2018-09-18 19:36:43 -04:00
|
|
|
|
2018-11-28 17:18:09 -05:00
|
|
|
Owner?.DecrementThreadCountAndTerminateIfZero();
|
2018-02-04 18:08:20 -05:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|