2018-10-30 21:43:02 -04:00
|
|
|
using ChocolArm64.Decoders;
|
2019-04-26 00:55:12 -04:00
|
|
|
using ChocolArm64.IntermediateRepresentation;
|
2018-10-30 21:43:02 -04:00
|
|
|
using ChocolArm64.Memory;
|
2019-02-24 02:24:35 -05:00
|
|
|
using ChocolArm64.State;
|
2018-10-30 21:43:02 -04:00
|
|
|
using ChocolArm64.Translation;
|
|
|
|
using System;
|
|
|
|
using System.Reflection.Emit;
|
2019-02-24 02:24:35 -05:00
|
|
|
using System.Runtime.Intrinsics.X86;
|
2018-10-30 21:43:02 -04:00
|
|
|
|
|
|
|
namespace ChocolArm64.Instructions
|
|
|
|
{
|
|
|
|
static class InstEmitMemoryHelper
|
|
|
|
{
|
2019-02-24 02:24:35 -05:00
|
|
|
private static int _tempIntAddress = ILEmitterCtx.GetIntTempIndex();
|
|
|
|
private static int _tempIntValue = ILEmitterCtx.GetIntTempIndex();
|
|
|
|
private static int _tempIntPtAddr = ILEmitterCtx.GetIntTempIndex();
|
|
|
|
private static int _tempVecValue = ILEmitterCtx.GetVecTempIndex();
|
|
|
|
|
2018-10-30 21:43:02 -04:00
|
|
|
private enum Extension
|
|
|
|
{
|
|
|
|
Zx,
|
|
|
|
Sx32,
|
|
|
|
Sx64
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitReadZxCall(ILEmitterCtx context, int size)
|
|
|
|
{
|
|
|
|
EmitReadCall(context, Extension.Zx, size);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitReadSx32Call(ILEmitterCtx context, int size)
|
|
|
|
{
|
|
|
|
EmitReadCall(context, Extension.Sx32, size);
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitReadSx64Call(ILEmitterCtx context, int size)
|
|
|
|
{
|
|
|
|
EmitReadCall(context, Extension.Sx64, size);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitReadCall(ILEmitterCtx context, Extension ext, int size)
|
|
|
|
{
|
2019-07-01 22:39:22 -04:00
|
|
|
// Save the address into a temp.
|
2019-02-24 02:24:35 -05:00
|
|
|
context.EmitStint(_tempIntAddress);
|
2018-10-30 21:43:02 -04:00
|
|
|
|
2019-02-24 02:24:35 -05:00
|
|
|
bool isSimd = IsSimd(context);
|
2018-10-30 21:43:02 -04:00
|
|
|
|
|
|
|
if (size < 0 || size > (isSimd ? 4 : 3))
|
|
|
|
{
|
|
|
|
throw new ArgumentOutOfRangeException(nameof(size));
|
|
|
|
}
|
|
|
|
|
|
|
|
if (isSimd)
|
|
|
|
{
|
2019-02-24 02:24:35 -05:00
|
|
|
if (context.Tier == TranslationTier.Tier0 || !Sse2.IsSupported || size < 2)
|
|
|
|
{
|
|
|
|
EmitReadVectorFallback(context, size);
|
|
|
|
}
|
|
|
|
else
|
2018-10-30 21:43:02 -04:00
|
|
|
{
|
2019-02-24 02:24:35 -05:00
|
|
|
EmitReadVector(context, size);
|
2018-10-30 21:43:02 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2019-02-24 02:24:35 -05:00
|
|
|
if (context.Tier == TranslationTier.Tier0)
|
2018-10-30 21:43:02 -04:00
|
|
|
{
|
2019-02-24 02:24:35 -05:00
|
|
|
EmitReadIntFallback(context, size);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
EmitReadInt(context, size);
|
2018-10-30 21:43:02 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!isSimd)
|
|
|
|
{
|
|
|
|
if (ext == Extension.Sx32 ||
|
|
|
|
ext == Extension.Sx64)
|
|
|
|
{
|
|
|
|
switch (size)
|
|
|
|
{
|
|
|
|
case 0: context.Emit(OpCodes.Conv_I1); break;
|
|
|
|
case 1: context.Emit(OpCodes.Conv_I2); break;
|
|
|
|
case 2: context.Emit(OpCodes.Conv_I4); break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (size < 3)
|
|
|
|
{
|
|
|
|
context.Emit(ext == Extension.Sx64
|
|
|
|
? OpCodes.Conv_I8
|
|
|
|
: OpCodes.Conv_U8);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
public static void EmitWriteCall(ILEmitterCtx context, int size)
|
|
|
|
{
|
2019-02-24 02:24:35 -05:00
|
|
|
bool isSimd = IsSimd(context);
|
2018-10-30 21:43:02 -04:00
|
|
|
|
2019-07-01 22:39:22 -04:00
|
|
|
// Save the value into a temp.
|
2019-02-24 02:24:35 -05:00
|
|
|
if (isSimd)
|
2018-10-30 21:43:02 -04:00
|
|
|
{
|
2019-02-24 02:24:35 -05:00
|
|
|
context.EmitStvec(_tempVecValue);
|
2018-10-30 21:43:02 -04:00
|
|
|
}
|
2019-02-24 02:24:35 -05:00
|
|
|
else
|
|
|
|
{
|
|
|
|
context.EmitStint(_tempIntValue);
|
|
|
|
}
|
|
|
|
|
2019-07-01 22:39:22 -04:00
|
|
|
// Save the address into a temp.
|
2019-02-24 02:24:35 -05:00
|
|
|
context.EmitStint(_tempIntAddress);
|
2018-10-30 21:43:02 -04:00
|
|
|
|
2019-02-24 02:24:35 -05:00
|
|
|
if (size < 0 || size > (isSimd ? 4 : 3))
|
2018-10-30 21:43:02 -04:00
|
|
|
{
|
2019-02-24 02:24:35 -05:00
|
|
|
throw new ArgumentOutOfRangeException(nameof(size));
|
2018-10-30 21:43:02 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
if (isSimd)
|
|
|
|
{
|
2019-02-24 02:24:35 -05:00
|
|
|
if (context.Tier == TranslationTier.Tier0 || !Sse2.IsSupported || size < 2)
|
|
|
|
{
|
|
|
|
EmitWriteVectorFallback(context, size);
|
|
|
|
}
|
|
|
|
else
|
2018-10-30 21:43:02 -04:00
|
|
|
{
|
2019-02-24 02:24:35 -05:00
|
|
|
EmitWriteVector(context, size);
|
2018-10-30 21:43:02 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2019-02-24 02:24:35 -05:00
|
|
|
if (context.Tier == TranslationTier.Tier0)
|
2018-10-30 21:43:02 -04:00
|
|
|
{
|
2019-02-24 02:24:35 -05:00
|
|
|
EmitWriteIntFallback(context, size);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
EmitWriteInt(context, size);
|
2018-10-30 21:43:02 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-02-24 02:24:35 -05:00
|
|
|
private static bool IsSimd(ILEmitterCtx context)
|
2018-10-30 21:43:02 -04:00
|
|
|
{
|
|
|
|
return context.CurrOp is IOpCodeSimd64 &&
|
|
|
|
!(context.CurrOp is OpCodeSimdMemMs64 ||
|
|
|
|
context.CurrOp is OpCodeSimdMemSs64);
|
|
|
|
}
|
2019-02-24 02:24:35 -05:00
|
|
|
|
|
|
|
private static void EmitReadInt(ILEmitterCtx context, int size)
|
|
|
|
{
|
|
|
|
EmitAddressCheck(context, size);
|
|
|
|
|
|
|
|
ILLabel lblFastPath = new ILLabel();
|
|
|
|
ILLabel lblSlowPath = new ILLabel();
|
|
|
|
ILLabel lblEnd = new ILLabel();
|
|
|
|
|
|
|
|
context.Emit(OpCodes.Brfalse_S, lblFastPath);
|
|
|
|
|
|
|
|
context.MarkLabel(lblSlowPath);
|
|
|
|
|
|
|
|
EmitReadIntFallback(context, size);
|
|
|
|
|
|
|
|
context.Emit(OpCodes.Br, lblEnd);
|
|
|
|
|
|
|
|
context.MarkLabel(lblFastPath);
|
|
|
|
|
|
|
|
EmitPtPointerLoad(context, lblSlowPath);
|
|
|
|
|
|
|
|
switch (size)
|
|
|
|
{
|
|
|
|
case 0: context.Emit(OpCodes.Ldind_U1); break;
|
|
|
|
case 1: context.Emit(OpCodes.Ldind_U2); break;
|
|
|
|
case 2: context.Emit(OpCodes.Ldind_U4); break;
|
|
|
|
case 3: context.Emit(OpCodes.Ldind_I8); break;
|
|
|
|
}
|
|
|
|
|
|
|
|
context.MarkLabel(lblEnd);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitReadVector(ILEmitterCtx context, int size)
|
|
|
|
{
|
|
|
|
EmitAddressCheck(context, size);
|
|
|
|
|
|
|
|
ILLabel lblFastPath = new ILLabel();
|
|
|
|
ILLabel lblSlowPath = new ILLabel();
|
|
|
|
ILLabel lblEnd = new ILLabel();
|
|
|
|
|
|
|
|
context.Emit(OpCodes.Brfalse_S, lblFastPath);
|
|
|
|
|
|
|
|
context.MarkLabel(lblSlowPath);
|
|
|
|
|
|
|
|
EmitReadVectorFallback(context, size);
|
|
|
|
|
|
|
|
context.Emit(OpCodes.Br, lblEnd);
|
|
|
|
|
|
|
|
context.MarkLabel(lblFastPath);
|
|
|
|
|
|
|
|
EmitPtPointerLoad(context, lblSlowPath);
|
|
|
|
|
|
|
|
switch (size)
|
|
|
|
{
|
2019-02-25 18:46:34 -05:00
|
|
|
case 2: context.EmitCall(typeof(Sse), nameof(Sse.LoadScalarVector128)); break;
|
2019-02-24 02:24:35 -05:00
|
|
|
|
|
|
|
case 3:
|
|
|
|
{
|
|
|
|
Type[] types = new Type[] { typeof(double*) };
|
|
|
|
|
|
|
|
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.LoadScalarVector128), types));
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2019-02-25 18:46:34 -05:00
|
|
|
case 4: context.EmitCall(typeof(Sse), nameof(Sse.LoadAlignedVector128)); break;
|
2019-02-24 02:24:35 -05:00
|
|
|
|
|
|
|
throw new InvalidOperationException($"Invalid vector load size of {1 << size} bytes.");
|
|
|
|
}
|
|
|
|
|
|
|
|
context.MarkLabel(lblEnd);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitWriteInt(ILEmitterCtx context, int size)
|
|
|
|
{
|
|
|
|
EmitAddressCheck(context, size);
|
|
|
|
|
|
|
|
ILLabel lblFastPath = new ILLabel();
|
|
|
|
ILLabel lblSlowPath = new ILLabel();
|
|
|
|
ILLabel lblEnd = new ILLabel();
|
|
|
|
|
|
|
|
context.Emit(OpCodes.Brfalse_S, lblFastPath);
|
|
|
|
|
|
|
|
context.MarkLabel(lblSlowPath);
|
|
|
|
|
|
|
|
EmitWriteIntFallback(context, size);
|
|
|
|
|
|
|
|
context.Emit(OpCodes.Br, lblEnd);
|
|
|
|
|
|
|
|
context.MarkLabel(lblFastPath);
|
|
|
|
|
|
|
|
EmitPtPointerLoad(context, lblSlowPath);
|
|
|
|
|
|
|
|
context.EmitLdint(_tempIntValue);
|
|
|
|
|
|
|
|
if (size < 3)
|
|
|
|
{
|
|
|
|
context.Emit(OpCodes.Conv_U4);
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (size)
|
|
|
|
{
|
|
|
|
case 0: context.Emit(OpCodes.Stind_I1); break;
|
|
|
|
case 1: context.Emit(OpCodes.Stind_I2); break;
|
|
|
|
case 2: context.Emit(OpCodes.Stind_I4); break;
|
|
|
|
case 3: context.Emit(OpCodes.Stind_I8); break;
|
|
|
|
}
|
|
|
|
|
|
|
|
context.MarkLabel(lblEnd);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitWriteVector(ILEmitterCtx context, int size)
|
|
|
|
{
|
|
|
|
EmitAddressCheck(context, size);
|
|
|
|
|
|
|
|
ILLabel lblFastPath = new ILLabel();
|
|
|
|
ILLabel lblSlowPath = new ILLabel();
|
|
|
|
ILLabel lblEnd = new ILLabel();
|
|
|
|
|
|
|
|
context.Emit(OpCodes.Brfalse_S, lblFastPath);
|
|
|
|
|
|
|
|
context.MarkLabel(lblSlowPath);
|
|
|
|
|
|
|
|
EmitWriteVectorFallback(context, size);
|
|
|
|
|
|
|
|
context.Emit(OpCodes.Br, lblEnd);
|
|
|
|
|
|
|
|
context.MarkLabel(lblFastPath);
|
|
|
|
|
|
|
|
EmitPtPointerLoad(context, lblSlowPath);
|
|
|
|
|
|
|
|
context.EmitLdvec(_tempVecValue);
|
|
|
|
|
|
|
|
switch (size)
|
|
|
|
{
|
2019-02-25 18:46:34 -05:00
|
|
|
case 2: context.EmitCall(typeof(Sse), nameof(Sse.StoreScalar)); break;
|
|
|
|
case 3: context.EmitCall(typeof(Sse2), nameof(Sse2.StoreScalar)); break;
|
|
|
|
case 4: context.EmitCall(typeof(Sse), nameof(Sse.StoreAligned)); break;
|
2019-02-24 02:24:35 -05:00
|
|
|
|
|
|
|
default: throw new InvalidOperationException($"Invalid vector store size of {1 << size} bytes.");
|
|
|
|
}
|
|
|
|
|
|
|
|
context.MarkLabel(lblEnd);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitAddressCheck(ILEmitterCtx context, int size)
|
|
|
|
{
|
|
|
|
long addressCheckMask = ~(context.Memory.AddressSpaceSize - 1);
|
|
|
|
|
|
|
|
addressCheckMask |= (1u << size) - 1;
|
|
|
|
|
|
|
|
context.EmitLdint(_tempIntAddress);
|
|
|
|
|
|
|
|
context.EmitLdc_I(addressCheckMask);
|
|
|
|
|
|
|
|
context.Emit(OpCodes.And);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitPtPointerLoad(ILEmitterCtx context, ILLabel lblFallbackPath)
|
|
|
|
{
|
|
|
|
context.EmitLdc_I8(context.Memory.PageTable.ToInt64());
|
|
|
|
|
|
|
|
context.Emit(OpCodes.Conv_I);
|
|
|
|
|
|
|
|
int bit = MemoryManager.PageBits;
|
|
|
|
|
|
|
|
do
|
|
|
|
{
|
|
|
|
context.EmitLdint(_tempIntAddress);
|
|
|
|
|
|
|
|
if (context.CurrOp.RegisterSize == RegisterSize.Int32)
|
|
|
|
{
|
|
|
|
context.Emit(OpCodes.Conv_U8);
|
|
|
|
}
|
|
|
|
|
|
|
|
context.EmitLsr(bit);
|
|
|
|
|
|
|
|
bit += context.Memory.PtLevelBits;
|
|
|
|
|
|
|
|
if (bit < context.Memory.AddressSpaceBits)
|
|
|
|
{
|
|
|
|
context.EmitLdc_I8(context.Memory.PtLevelMask);
|
|
|
|
|
|
|
|
context.Emit(OpCodes.And);
|
|
|
|
}
|
|
|
|
|
|
|
|
context.EmitLdc_I8(IntPtr.Size);
|
|
|
|
|
|
|
|
context.Emit(OpCodes.Mul);
|
|
|
|
context.Emit(OpCodes.Conv_I);
|
|
|
|
context.Emit(OpCodes.Add);
|
|
|
|
context.Emit(OpCodes.Ldind_I);
|
|
|
|
}
|
|
|
|
while (bit < context.Memory.AddressSpaceBits);
|
|
|
|
|
|
|
|
if (!context.Memory.HasWriteWatchSupport)
|
|
|
|
{
|
|
|
|
context.Emit(OpCodes.Conv_U8);
|
|
|
|
|
|
|
|
context.EmitStint(_tempIntPtAddr);
|
|
|
|
context.EmitLdint(_tempIntPtAddr);
|
|
|
|
|
|
|
|
context.EmitLdc_I8(MemoryManager.PteFlagsMask);
|
|
|
|
|
|
|
|
context.Emit(OpCodes.And);
|
|
|
|
|
|
|
|
context.Emit(OpCodes.Brtrue, lblFallbackPath);
|
|
|
|
|
|
|
|
context.EmitLdint(_tempIntPtAddr);
|
|
|
|
|
|
|
|
context.Emit(OpCodes.Conv_I);
|
|
|
|
}
|
|
|
|
|
|
|
|
context.EmitLdint(_tempIntAddress);
|
|
|
|
|
|
|
|
context.EmitLdc_I(MemoryManager.PageMask);
|
|
|
|
|
|
|
|
context.Emit(OpCodes.And);
|
|
|
|
context.Emit(OpCodes.Conv_I);
|
|
|
|
context.Emit(OpCodes.Add);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitReadIntFallback(ILEmitterCtx context, int size)
|
|
|
|
{
|
|
|
|
context.EmitLdarg(TranslatedSub.MemoryArgIdx);
|
|
|
|
context.EmitLdint(_tempIntAddress);
|
|
|
|
|
|
|
|
if (context.CurrOp.RegisterSize == RegisterSize.Int32)
|
|
|
|
{
|
|
|
|
context.Emit(OpCodes.Conv_U8);
|
|
|
|
}
|
|
|
|
|
|
|
|
string fallbackMethodName = null;
|
|
|
|
|
|
|
|
switch (size)
|
|
|
|
{
|
|
|
|
case 0: fallbackMethodName = nameof(MemoryManager.ReadByte); break;
|
|
|
|
case 1: fallbackMethodName = nameof(MemoryManager.ReadUInt16); break;
|
|
|
|
case 2: fallbackMethodName = nameof(MemoryManager.ReadUInt32); break;
|
|
|
|
case 3: fallbackMethodName = nameof(MemoryManager.ReadUInt64); break;
|
|
|
|
}
|
|
|
|
|
|
|
|
context.EmitCall(typeof(MemoryManager), fallbackMethodName);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitReadVectorFallback(ILEmitterCtx context, int size)
|
|
|
|
{
|
|
|
|
context.EmitLdarg(TranslatedSub.MemoryArgIdx);
|
|
|
|
context.EmitLdint(_tempIntAddress);
|
|
|
|
|
|
|
|
if (context.CurrOp.RegisterSize == RegisterSize.Int32)
|
|
|
|
{
|
|
|
|
context.Emit(OpCodes.Conv_U8);
|
|
|
|
}
|
|
|
|
|
|
|
|
string fallbackMethodName = null;
|
|
|
|
|
|
|
|
switch (size)
|
|
|
|
{
|
|
|
|
case 0: fallbackMethodName = nameof(MemoryManager.ReadVector8); break;
|
|
|
|
case 1: fallbackMethodName = nameof(MemoryManager.ReadVector16); break;
|
|
|
|
case 2: fallbackMethodName = nameof(MemoryManager.ReadVector32); break;
|
|
|
|
case 3: fallbackMethodName = nameof(MemoryManager.ReadVector64); break;
|
|
|
|
case 4: fallbackMethodName = nameof(MemoryManager.ReadVector128); break;
|
|
|
|
}
|
|
|
|
|
|
|
|
context.EmitCall(typeof(MemoryManager), fallbackMethodName);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitWriteIntFallback(ILEmitterCtx context, int size)
|
|
|
|
{
|
|
|
|
context.EmitLdarg(TranslatedSub.MemoryArgIdx);
|
|
|
|
context.EmitLdint(_tempIntAddress);
|
|
|
|
|
|
|
|
if (context.CurrOp.RegisterSize == RegisterSize.Int32)
|
|
|
|
{
|
|
|
|
context.Emit(OpCodes.Conv_U8);
|
|
|
|
}
|
|
|
|
|
|
|
|
context.EmitLdint(_tempIntValue);
|
|
|
|
|
|
|
|
if (size < 3)
|
|
|
|
{
|
|
|
|
context.Emit(OpCodes.Conv_U4);
|
|
|
|
}
|
|
|
|
|
|
|
|
string fallbackMethodName = null;
|
|
|
|
|
|
|
|
switch (size)
|
|
|
|
{
|
|
|
|
case 0: fallbackMethodName = nameof(MemoryManager.WriteByte); break;
|
|
|
|
case 1: fallbackMethodName = nameof(MemoryManager.WriteUInt16); break;
|
|
|
|
case 2: fallbackMethodName = nameof(MemoryManager.WriteUInt32); break;
|
|
|
|
case 3: fallbackMethodName = nameof(MemoryManager.WriteUInt64); break;
|
|
|
|
}
|
|
|
|
|
|
|
|
context.EmitCall(typeof(MemoryManager), fallbackMethodName);
|
|
|
|
}
|
|
|
|
|
|
|
|
private static void EmitWriteVectorFallback(ILEmitterCtx context, int size)
|
|
|
|
{
|
|
|
|
context.EmitLdarg(TranslatedSub.MemoryArgIdx);
|
|
|
|
context.EmitLdint(_tempIntAddress);
|
|
|
|
|
|
|
|
if (context.CurrOp.RegisterSize == RegisterSize.Int32)
|
|
|
|
{
|
|
|
|
context.Emit(OpCodes.Conv_U8);
|
|
|
|
}
|
|
|
|
|
|
|
|
context.EmitLdvec(_tempVecValue);
|
|
|
|
|
|
|
|
string fallbackMethodName = null;
|
|
|
|
|
|
|
|
switch (size)
|
|
|
|
{
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 14:56:22 -04:00
|
|
|
case 0: fallbackMethodName = nameof(MemoryManager.WriteVector8); break;
|
|
|
|
case 1: fallbackMethodName = nameof(MemoryManager.WriteVector16); break;
|
|
|
|
case 2: fallbackMethodName = nameof(MemoryManager.WriteVector32); break;
|
|
|
|
case 3: fallbackMethodName = nameof(MemoryManager.WriteVector64); break;
|
|
|
|
case 4: fallbackMethodName = nameof(MemoryManager.WriteVector128Internal); break;
|
2019-02-24 02:24:35 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
context.EmitCall(typeof(MemoryManager), fallbackMethodName);
|
|
|
|
}
|
2018-10-30 21:43:02 -04:00
|
|
|
}
|
|
|
|
}
|