2018-10-30 21:43:02 -04:00
|
|
|
using ChocolArm64.State;
|
|
|
|
using System.Reflection.Emit;
|
|
|
|
|
|
|
|
namespace ChocolArm64.Translation
|
|
|
|
{
|
2018-12-10 19:58:52 -05:00
|
|
|
struct ILOpCodeLoad : IILEmit
|
2018-10-30 21:43:02 -04:00
|
|
|
{
|
2019-02-27 21:03:31 -05:00
|
|
|
public int Index { get; }
|
2018-10-30 21:43:02 -04:00
|
|
|
|
2019-02-27 21:03:31 -05:00
|
|
|
public VarType VarType { get; }
|
2018-10-30 21:43:02 -04:00
|
|
|
|
2019-02-27 21:03:31 -05:00
|
|
|
public RegisterSize RegisterSize { get; }
|
2018-10-30 21:43:02 -04:00
|
|
|
|
2019-02-27 21:03:31 -05:00
|
|
|
public ILOpCodeLoad(int index, VarType varType, RegisterSize registerSize = 0)
|
2018-10-30 21:43:02 -04:00
|
|
|
{
|
|
|
|
Index = index;
|
2019-02-27 21:03:31 -05:00
|
|
|
VarType = varType;
|
2018-10-30 21:43:02 -04:00
|
|
|
RegisterSize = registerSize;
|
|
|
|
}
|
|
|
|
|
2018-12-10 19:58:52 -05:00
|
|
|
public void Emit(ILMethodBuilder context)
|
2018-10-30 21:43:02 -04:00
|
|
|
{
|
2019-02-27 21:03:31 -05:00
|
|
|
switch (VarType)
|
2018-10-30 21:43:02 -04:00
|
|
|
{
|
2019-02-27 21:03:31 -05:00
|
|
|
case VarType.Arg: context.Generator.EmitLdarg(Index); break;
|
2018-10-30 21:43:02 -04:00
|
|
|
|
2019-02-27 21:03:31 -05:00
|
|
|
case VarType.Flag: EmitLdloc(context, Index, RegisterType.Flag); break;
|
|
|
|
case VarType.Int: EmitLdloc(context, Index, RegisterType.Int); break;
|
|
|
|
case VarType.Vector: EmitLdloc(context, Index, RegisterType.Vector); break;
|
2018-10-30 21:43:02 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-12-10 19:58:52 -05:00
|
|
|
private void EmitLdloc(ILMethodBuilder context, int index, RegisterType registerType)
|
2018-10-30 21:43:02 -04:00
|
|
|
{
|
|
|
|
Register reg = new Register(index, registerType);
|
|
|
|
|
|
|
|
context.Generator.EmitLdloc(context.GetLocalIndex(reg));
|
|
|
|
|
|
|
|
if (registerType == RegisterType.Int &&
|
|
|
|
RegisterSize == RegisterSize.Int32)
|
|
|
|
{
|
|
|
|
context.Generator.Emit(OpCodes.Conv_U4);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|