2019-01-24 20:59:53 -05:00
|
|
|
using ChocolArm64.Instructions;
|
|
|
|
|
|
|
|
namespace ChocolArm64.Decoders
|
|
|
|
{
|
Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)
* Rename some opcode classes and flag masks for consistency
* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations
* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC
* Re-align arm32 instructions on the opcode table
2019-01-29 11:06:11 -05:00
|
|
|
class OpCodeT16AluImm8 : OpCodeT16, IOpCode32Alu
|
2019-01-24 20:59:53 -05:00
|
|
|
{
|
|
|
|
private int _rdn;
|
|
|
|
|
|
|
|
public int Rd => _rdn;
|
|
|
|
public int Rn => _rdn;
|
|
|
|
|
|
|
|
public bool SetFlags => false;
|
|
|
|
|
|
|
|
public int Imm { get; private set; }
|
|
|
|
|
Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)
* Rename some opcode classes and flag masks for consistency
* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations
* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC
* Re-align arm32 instructions on the opcode table
2019-01-29 11:06:11 -05:00
|
|
|
public OpCodeT16AluImm8(Inst inst, long position, int opCode) : base(inst, position, opCode)
|
2019-01-24 20:59:53 -05:00
|
|
|
{
|
|
|
|
Imm = (opCode >> 0) & 0xff;
|
|
|
|
_rdn = (opCode >> 8) & 0x7;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|